JPS58111415A - Offset cancelling circuit for differential amplifier - Google Patents

Offset cancelling circuit for differential amplifier

Info

Publication number
JPS58111415A
JPS58111415A JP56207980A JP20798081A JPS58111415A JP S58111415 A JPS58111415 A JP S58111415A JP 56207980 A JP56207980 A JP 56207980A JP 20798081 A JP20798081 A JP 20798081A JP S58111415 A JPS58111415 A JP S58111415A
Authority
JP
Japan
Prior art keywords
differential amplifier
offset
output
amplifier
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56207980A
Other languages
Japanese (ja)
Inventor
Sunao Nakamura
直 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56207980A priority Critical patent/JPS58111415A/en
Publication of JPS58111415A publication Critical patent/JPS58111415A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the operating point from being fixed and the operating range from being narrowered, by feeding-back a DC output of an amplifier negatively to an input side and zeroing a DC offset automatically. CONSTITUTION:DC currents I1i, I2i being equal normally are applied to input terminal IN1, IN2 of a differential amplifier 1 via impedance ZA, ZB from a bias voltage VCT, and when ZA, ZB are equal with each other, potentials at base connecting points A, B, collector connecting points C, D, and output side connecting points E, F of transistors (TR) 1, 2 are equal and a DC offset is zero. While ZA>ZB, the base potential of the TR1 is lower than that of the TR2. This potential difference is amplified and applied to an offset detector 21 of a differential amplifier 2 as a DC offset voltage. As a result, the amplifier 2 feeds back the DC output negatively to the input side and the base potential of the TR1 is made higher than that of the TR2, allowing to zero the DC offset voltage automatically.

Description

【発明の詳細な説明】 (り発明の技術分計 本発明は直流オーツセットキャンセル回路1特に差動増
幅器からの出力信号の直流オフセットを自動的にキャン
セルする回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DC auto-set canceling circuit 1, particularly to a circuit that automatically cancels a DC offset of an output signal from a differential amplifier.

(2)  技術の背景 磁気ディスク#10ヘッドとして、磁界の変化によりイ
ンピーダンスが変化する性質を有する1グネツトレジス
テイブ素子が萬感度の磁気電気変換が可能であるため、
広く利用され始めている。このようなiダネットレジス
ティブ素子に一定のバイアス11を流を流して信号の動
作点を定め、取〕出した信号を差動増幅器によシ増幅し
て次段の回路に接続している。
(2) Background of the technology As the magnetic disk #10 head, a 1-magnetic resistive element whose impedance changes with changes in the magnetic field is capable of magnetoelectric conversion with infinite sensitivity.
It is beginning to be widely used. A constant bias 11 is applied to such an i-Dannet resistive element to determine the operating point of the signal, and the extracted signal is amplified by a differential amplifier and connected to the next stage circuit.

(3)従来技術と問題点 第1図紘一般的な差動増幅器を示し、人力信号FiXN
1.xN2よ!:*入夛増幅さiて0UT1゜0UT2
に出力される。VCCは正電源、VEICは負電源を示
し、R1,R2は人力終燗抵抗を示す。差動増幅iio
*m段は、トランジスタQl。
(3) Prior art and problems Figure 1 shows a general differential amplifier, and the human input signal FiXN
1. xN2! :*Increased amplification 0UT1゜0UT2
is output to. VCC is a positive power supply, VEIC is a negative power supply, and R1 and R2 are human termination resistances. differential amplification io
*The m stage is a transistor Ql.

Q2、抵抗R5,R4、電流源11、増幅−Bによ多構
成される。
Q2, resistors R5 and R4, current source 11, and amplifier-B.

この機な、従来の差動増幅器は内部的要因と外部的要因
によ)オフセットを生じ蛎作点を変動させることがあっ
た。即ち差動対を構成する2つのトランジスタQ、、Q
、の特性上の相異めるいは入力端子IN□IN、に接続
された信号源の変化、例えば1紀のマグネットレジステ
イブ業子MRを構成する2つのインピーダンスのアンバ
ランスが主な要因となり、1112図に示す差動増幅器
の人力電圧vX)Iと出力電圧V。Vtの静特性曲線上
において、無情号時に上述し九要因により入力端子IN
、。
In this case, conventional differential amplifiers may generate offsets (due to internal and external factors), causing fluctuations in the production point. In other words, two transistors Q, ,Q forming a differential pair
, or changes in the signal source connected to the input terminal IN□IN, for example, the imbalance of the two impedances that make up the 1st generation magnet resistive Giko MR is the main factor. , 1112 The human power voltage vX) I and the output voltage V of the differential amplifier shown in FIG. On the static characteristic curve of Vt, when there is no signal, the input terminal IN due to the nine factors mentioned above.
,.

INjK直流的な差動電圧Δv1が加わっていると、オ
フ七ツF電圧ΔV・が発生し動作点が本来の0点から偏
位してPAK移動することになる。仁の結果、静特性f
!4軸上の線形部分AB内に信号が収壕らなくな〉、人
力信号8Kに対して出力信号8゜は否んだ波形となって
破線で示す部分だけ忠実に再現されなくなる。すなわち
ダイナ建ツクレンジが狭くなってしtう。
When INjK DC-like differential voltage Δv1 is applied, an off-seven F voltage ΔV· is generated, and the operating point deviates from the original 0 point and moves to PAK. As a result, the static characteristic f
! The signal no longer fits within the linear portion AB on the 4th axis, and the output signal 8° becomes a waveform that is rejected with respect to the human input signal 8K, and only the portion shown by the broken line is not faithfully reproduced. In other words, the dynamic range becomes narrower.

このように従来技術においては、直流分オフセラ>Kよ
)動作点が変動して入力信号に対して出力信号が忠実に
再現されず動作範囲が狭くなるという間一点かあ0え。
As described above, in the conventional technology, the operating point fluctuates (DC component offset > K), and the output signal is not faithfully reproduced with respect to the input signal, resulting in a narrowing of the operating range.

+4)  A明の目的 本発明の目的轄、差動増幅器の直流出力を入力−へ負帰
還させて直流オフセットを自動的に0にすることによシ
、動作点を固定し動作範囲の挾少を敵前することにある
+4) Purpose of A: The purpose of the present invention is to fix the operating point and narrow the operating range by negatively feedbacking the DC output of a differential amplifier to the negative input and automatically setting the DC offset to 0. The goal is to confront the enemy.

(5)発明の構成 本発明によれば差動増幅器の差動出力を人力とし、該差
動増m器の人力信号I#波数より十分低いl#波数特性
を有し該差動出力に含すれる直流成分を増幅し誤差信号
として出方する増幅器と該誤差信号に応じて該差動増幅
器のそれぞれの人力端に加えるバイアス電流を変化する
バイアス電流源よ)成ることを特徴とする差動増幅器の
オフセットキャンセル回路が提供される。
(5) Structure of the Invention According to the present invention, the differential output of a differential amplifier is human-powered, and the differential output has l# wavenumber characteristics sufficiently lower than the I# wavenumber of the human-powered signal of the differential amplifier. A differential amplifier comprising: an amplifier that amplifies a DC component that is lost and outputs it as an error signal; and a bias current source that changes a bias current applied to each input terminal of the differential amplifier according to the error signal. An amplifier offset cancellation circuit is provided.

(6)発明の実施例 以下、本発明を実施例にょシ添付図面を4呻して説明す
る。
(6) Embodiments of the Invention The present invention will be described below with reference to embodiments and the accompanying drawings.

IN5図は本発明にょる差動増m器のオフセットキャン
セル回路の構成図である。本発明回路は人力端子IN1
. IN、から入力したマグネットレジステイブ素子M
Rからの各信号の差を増幅して出力端子0UTI、ou
’r、がら取)出す第1差動増m1iillと、誼出力
端子OUT  ouT、の出力のうちtl#11 渡分のみを増幅して上記人力端子IN、、IN2に負帰
還させる帰(作用を有する#I2差動増%l器2とから
構成されている。
Figure IN5 is a configuration diagram of an offset canceling circuit of a differential amplifier according to the present invention. The circuit of the present invention has a human power terminal IN1.
.. Magnetic resistive element M input from IN
The difference between each signal from R is amplified and the output terminal 0UTI, ou
Out of the output from the first differential amplifier m1iill and output terminal OUT outT, only the tl#11 portion is amplified and negatively fed back to the human input terminals IN, IN2. #I2 differential intensifier 2.

111差動増暢1110人力噛子IN、、IN、には!
ダネットレジスティブ素子MR(以下MRとする)が接
続されている。
111 Differential increase 1110 Human power bite IN,, IN, to!
A Dunnett resistive element MR (hereinafter referred to as MR) is connected.

上記MRはインピーダンスZAIZIを有し、図示する
様に1ンタータツプに電圧VCTが印加され、電tIL
122 K X D’ttL”t’tL Il 1. 
Il i Oハ(7ス電流が供給される。抵抗R,,R
,は増幅器バイアスの九めの40で4畜しなくてもよい
が、その値は2ルzIIK比べ十分大きいものとする。
The above MR has an impedance ZAIZI, and as shown in the figure, a voltage VCT is applied to one tap, and a voltage tIL
122 K X D'ttL"t'tL Il 1.
Il i O (7 currents are supplied. Resistors R,, R
, does not need to be 4 times the ninth 40 of the amplifier bias, but its value should be sufficiently larger than 2 zIIK.

MRと磁束φ1が図のような方向で鎖交すると2ムは増
加し、zlは減少しその1!に比例した交流信号電圧Δ
V―がトランジスタTr1. Tr2のベースに加わる
When MR and magnetic flux φ1 interlink in the direction shown in the figure, 2m increases, zl decreases, and 1! AC signal voltage Δ proportional to
V- is the transistor Tr1. Joins the base of Tr2.

トランジスタfr1.Tr意  は差動対を梼成し、抵
抗R,,R40接続点C,Dから上記信号電圧ΔVs 
に比例し九電圧を増幅して取り出し、増幅器AMPへ供
給する。
Transistor fr1. The transistor forms a differential pair, and the above signal voltage ΔVs is applied from the resistors R, , R40 connection points C and D.
Amplify and take out nine voltages proportional to , and supply them to the amplifier AMP.

1112差動増幅182は1111差動増幅器1の出力
側接続点E、Fに接続され直流分VΣG、v、、 am
を増−して取シ出すオフセット検出回路21と、骸横田
回路21から入力され九オフセット分によりTr7. 
Tr@ 4p :Iレクタ電流変化させ接続点A、Bが
らMR3g子イ/キーダンスzA、zllを流れるバイ
アス電流を変化させるバイアス電流[22から構成され
ている。
The 1112 differential amplifier 182 is connected to the output side connection points E and F of the 1111 differential amplifier 1, and the DC component VΣG, v, , am
The offset detection circuit 21 increases and extracts the Tr7.
Tr@4p: Consists of a bias current [22] that changes the I-rector current and changes the bias current flowing through the MR3g I/key dances zA and zll from the connection points A and B.

オフセット検出回路21は篭圧瀘Vc@とIIE流櫨1
2s  )ツンジスタTry、Tr5及びTr4. T
r4を有している。抵抗R5Q R4は+41の差動増
幅器1の負荷として接続されるIN2の差動増幅111
2の影嗜を少なくする目的で挿入されており、i九コン
デンナCは抵抗a、、 R9と共にローパスフィルタを
構成し接続点E、Fから流入し良信号の交流分を除責す
る丸めに接続されている。
The offset detection circuit 21 is connected to the gate pressure Vc@ and the IIE Nagarashi 1.
2s) Tungista Try, Tr5 and Tr4. T
It has r4. Resistor R5Q R4 is the differential amplifier 111 of IN2 connected as a load of the differential amplifier 1 of +41
The i9 condenser C forms a low-pass filter together with the resistors a, R9, and is connected to the rounding that flows in from the connection points E and F to eliminate the alternating current component of the good signal. has been done.

バイアス電流源22を構成するトランジスタTr7.T
r6  のペースには負電源■。にょ夛抵抗R,,R,
。、ダイオードDを介して一定の電流が供給されておシ
、抵抗R,,R,はオフセント検出器21から供給され
た直流電流を電圧に変換してトランジスタT、、、Tr
、のニオツクに即席するようになっている。上記Ty7
.Tr−は既述したようにR・、R9に現れ走電圧変化
に比例してコレクタ電流を変化させる。すなわZA、Z
lへの直流バイアス電tJtを変える働暑がある。
Transistor Tr7. which constitutes bias current source 22. T
Negative power supply ■ for r6 pace. Nyota resistance R,,R,
. , a constant current is supplied through the diode D, and the resistors R, , R, convert the DC current supplied from the offset detector 21 into voltage, and the transistors T, , Tr
, has started to improvise on Niotsuku. Above Ty7
.. As mentioned above, Tr- appears at R.sup. and R9 and changes the collector current in proportion to the change in running voltage. Sunawa ZA, Z
There is a heat effect that changes the DC bias current tJt to l.

上記のように構成された本発明回路の動作は次の迩ルで
ある。
The operation of the circuit of the present invention configured as described above is as follows.

$11差動増!11の入力端子IN、、 IN、からは
通常は等しい直流電流1.、、I□ がバイアス電圧v
、TからZ、、Z、に供給され、Z、gZ、O時トッン
ジスタ”rl+〒r!Oベース接続点ム、B接続タム側
の接続点C,DI!に出力側の接・値点E、 F4D電
位は互いに等しい。即ち直流分のオフセットはOである
$11 differential increase! From the 11 input terminals IN, , IN, normally equal direct current 1. ,,I□ is the bias voltage v
, T is supplied to Z, , Z, and when Z, gZ, O, the output side contact/value point E is connected to the output side connection point C, DI! , F4D potentials are equal to each other, that is, the DC component offset is O.

しかし、MROZおzlKアンバ2ンスがあシz、>z
、o場合、Trlのベース1位はTr2のベース電位に
比べ下がる。この電位差は増幅され出力me、 FK直
直流オフフット電圧して現われ、停動増@−2のオフ竜
ット検出器21に供給されゐ。
However, the MROZOzlK imbalance is
, o, the base potential of Trl is lower than the base potential of Tr2. This potential difference is amplified and appears as an output me, FK DC off-foot voltage, which is supplied to the off-foot detector 21 of the stall increase@-2.

この場合(Z、>Z、)V、Gの電圧はV、。の電”圧
より大きい丸め”r4の電流はT、の電、流より大きく
な夛、バイアス電流+][22の抵抗R,、R,に流T
r@のエミッタの電位は〒、7の工ばツタ電位に対して
高くなるのでこの結果T1.のコレクタ電流l流はTr
7のそれよシ小さくなp、Trlのベース電位上Tr2
のベース電位に比べ高くする様に働く。すなわち出力オ
フ七ット電圧を0とする様に入力の111、I21 の
電流が自動的に変化する。
In this case, (Z,>Z,)V, the voltage of G is V,. The current of r4 is larger than the voltage of T, the bias current +][22 of resistors R,, R, has a current of T,
The potential of the emitter of r@ is higher than the potential of the emitter of 〒, 7, so as a result, T1. The collector current l current is Tr
7, p is smaller than that of Tr2, which is above the base potential of Trl.
It works to raise the base potential higher than the base potential of. That is, the currents of the inputs 111 and I21 automatically change so that the output OFF voltage becomes 0.

またMROZA=ZIIである場合でも、I、、。Also, even if MROZA=ZII, I, .

I21がアンバランスであった如、トランジスタTr1
. Tr2がアンバランスであっ九υ、R,、R4かア
ンバランスである様な場合、前記と同様出力に直流オフ
セット電圧が発生する。この場合でも、差動増幅器2が
働き、出力オフセット電圧をOとする様KI、、、I□
 O電流が自動的に変化する。
As I21 was unbalanced, transistor Tr1
.. When Tr2 is unbalanced and 9υ, R, and R4 are unbalanced, a DC offset voltage is generated at the output as described above. Even in this case, the differential amplifier 2 works so that the output offset voltage becomes O.
O current changes automatically.

尚、増幅器をモノリシックICf構成する場合、オフ七
ット検出器21のトランジスタTr3+’rr4として
周波数特性の低いラテツルPNP )う/ジスタを用い
ることによシコンデンサCは設けなくてすむ。
Incidentally, when the amplifier is configured as a monolithic ICf, the capacitor C can be omitted by using a latex PNP transistor with low frequency characteristics as the transistor Tr3+'rr4 of the off-circuit detector 21.

また嬉2図の実施例では増幅器AMPの田カーから負帰
還させているが、AMPの利得かはとんど1の場合出力
オフセットはムMPの前段のオフセットにより決定され
るので接続点CDから負帰還させてもよい。
In addition, in the embodiment shown in Figure 2, negative feedback is provided from the output circuit of the amplifier AMP, but if the gain of AMP is mostly 1, the output offset is determined by the offset of the previous stage of the amplifier AMP, so from the connection point CD Negative feedback may also be provided.

(7)発明の効果 上記の迩シ本発明によれば、差動増幅器の直流出力を入
力端へ負帰禰させて入力端のバイアス電流を変化させ直
流オフセラFを自動的にOにする仁とにより、ダイナイ
ックレンジの狭小を除去することができる。
(7) Effects of the Invention According to the present invention, the DC output of the differential amplifier is negatively fed back to the input terminal, the bias current at the input terminal is changed, and the DC offset circuit F is automatically set to O. This makes it possible to eliminate the narrowness of the dynaic range.

【図面の簡単な説明】[Brief explanation of drawings]

11図は従来の差動増幅器第2図は従来技術の人出力特
性図、第3図は本発明による差動増幅器のオフセットキ
ャン竜ル(ロ)路を示す構成図である。 1・・・I11差蛸増幅器、2・・・第2差動増幅器、
21・・・直流オフセット検出回路、22・・・バイア
ス電流源。 −8[
FIG. 11 is a conventional differential amplifier. FIG. 2 is a diagram showing the human output characteristics of the prior art. FIG. 3 is a block diagram showing the offset canceling path of the differential amplifier according to the present invention. 1... I11 differential amplifier, 2... Second differential amplifier,
21... DC offset detection circuit, 22... Bias current source. −8[

Claims (1)

【特許請求の範囲】[Claims] 幣動増幅器O差動出力を人力とし、諌差動増幅器の人力
信号1#波数より十分低い喝波数特性を有し峡差動出力
に含まれる直流成分を増幅し誤差信号として出力する増
aSと#誤差信号に応じて峡差動増lI器のそれぞれの
入力端に加えるバイアス電流を資化するバイアス電流源
よシaゐことを特徴とする差動増幅−のオフセットキャ
ンセル回路。
An increase aS that uses the O differential output of the differential amplifier as a human power, has a frequency characteristic sufficiently lower than the 1# wave number of the human power signal of the differential amplifier, and amplifies the DC component included in the differential output and outputs it as an error signal. #An offset canceling circuit for a differential amplifier, characterized in that it includes a bias current source that utilizes a bias current applied to each input terminal of a differential amplifier in response to an error signal.
JP56207980A 1981-12-24 1981-12-24 Offset cancelling circuit for differential amplifier Pending JPS58111415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56207980A JPS58111415A (en) 1981-12-24 1981-12-24 Offset cancelling circuit for differential amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56207980A JPS58111415A (en) 1981-12-24 1981-12-24 Offset cancelling circuit for differential amplifier

Publications (1)

Publication Number Publication Date
JPS58111415A true JPS58111415A (en) 1983-07-02

Family

ID=16548681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56207980A Pending JPS58111415A (en) 1981-12-24 1981-12-24 Offset cancelling circuit for differential amplifier

Country Status (1)

Country Link
JP (1) JPS58111415A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225665A (en) * 1985-03-30 1986-10-07 Toshiba Corp Output offset voltage detection circuit
JPS63284912A (en) * 1987-04-24 1988-11-22 アメリカン テレフオン アンド テレグラフ カムパニー Differential integrated circuit with variable offset
JPH01255306A (en) * 1988-04-04 1989-10-12 Hitachi Ltd Direct-current direct-coupled amplifier circuit
US5867062A (en) * 1996-11-20 1999-02-02 Nec Corporation DC-offset canceler circuit and differential amplifier circuit equipped therewith
US5999054A (en) * 1997-11-19 1999-12-07 Fujitsu Limited Differential amplifier circuit
US7298173B1 (en) 2004-10-26 2007-11-20 Marvell International Ltd. Slew rate control circuit for small computer system interface (SCSI) differential driver
KR101035344B1 (en) 2007-05-17 2011-05-20 내셔널 세미콘덕터 코포레이션 Autozeroing current feedback instrumentation amplifier

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225665A (en) * 1985-03-30 1986-10-07 Toshiba Corp Output offset voltage detection circuit
JPS63284912A (en) * 1987-04-24 1988-11-22 アメリカン テレフオン アンド テレグラフ カムパニー Differential integrated circuit with variable offset
JPH01255306A (en) * 1988-04-04 1989-10-12 Hitachi Ltd Direct-current direct-coupled amplifier circuit
US5867062A (en) * 1996-11-20 1999-02-02 Nec Corporation DC-offset canceler circuit and differential amplifier circuit equipped therewith
US5999054A (en) * 1997-11-19 1999-12-07 Fujitsu Limited Differential amplifier circuit
US7298173B1 (en) 2004-10-26 2007-11-20 Marvell International Ltd. Slew rate control circuit for small computer system interface (SCSI) differential driver
US7579873B1 (en) 2004-10-26 2009-08-25 Marvell International Ltd. Slew rate control circuit for small computer system interface (SCSI) differential driver
US7719314B1 (en) 2004-10-26 2010-05-18 Marvell International Ltd. Slew rate control circuit for small computer system interface (SCSI) differential driver
KR101035344B1 (en) 2007-05-17 2011-05-20 내셔널 세미콘덕터 코포레이션 Autozeroing current feedback instrumentation amplifier

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