JPS58109316U - doubler - Google Patents

doubler

Info

Publication number
JPS58109316U
JPS58109316U JP657382U JP657382U JPS58109316U JP S58109316 U JPS58109316 U JP S58109316U JP 657382 U JP657382 U JP 657382U JP 657382 U JP657382 U JP 657382U JP S58109316 U JPS58109316 U JP S58109316U
Authority
JP
Japan
Prior art keywords
terminal
half cycle
signal
voltage
intermediate terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP657382U
Other languages
Japanese (ja)
Inventor
南條 正則
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP657382U priority Critical patent/JPS58109316U/en
Publication of JPS58109316U publication Critical patent/JPS58109316U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の二逓倍装置の構成を示すブロック接続図
、第2図は第1図の逓倍器の構成を示す  2接続図、
第3図はこの考案の一実施例の構成を示す接続図である
。 図において、1Bは第1の制御端子、19は第2の制御
端子、2セは直列インビニダンス、23は中間端子、2
4は第1の増幅素子、27は第2の増幅素子、31は逓
倍端子である。なお、各図中、同一符号は同一または相
当部分を示すものとする。
FIG. 1 is a block connection diagram showing the configuration of a conventional doubler; FIG. 2 is a two-connection diagram showing the configuration of the multiplier in FIG. 1;
FIG. 3 is a connection diagram showing the configuration of an embodiment of this invention. In the figure, 1B is a first control terminal, 19 is a second control terminal, 2nd series is a series invinidance, 23 is an intermediate terminal, 2
4 is a first amplification element, 27 is a second amplification element, and 31 is a multiplication terminal. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部より正と負の電圧が半サイクルごとに、交互に繰返
す所定の周波数の交流信号が入力する第1と第2の制御
端子、直列インピーダン”スを通じて外部の直流電源に
接続され、上記直列インピーダンスに流れる電流の変動
によりその電位を変動させる中間端子、この中間端子に
接続され、上記第1の制御端子に接続され、上記交流信
号の正半波の電圧を増幅して正の半周期間に電流を流す
第1の増幅素子と、上記第2の制御端子に接続され、上
記交流信号の負半波の電圧を増幅して負の半周期間Iと
電流を流す第2の増幅奉子が互いに並列に接続された差
動増幅器、上記中間端子に接続された上記中間端子の正
の半周期と負の半周期間の電位変動を合成して上記所定
の周波数の二倍の周波数で変動する電圧を出力する逓倍
端子を備えζ上記入力交流信号の二倍の周波数の逓倍信
号を出力する二逓倍装置。
The first and second control terminals are connected to an external DC power supply through a series impedance, into which AC signals of a predetermined frequency are input, in which positive and negative voltages are alternately repeated every half cycle from the outside, and the series impedance is An intermediate terminal that changes the potential due to fluctuations in the current flowing through the terminal, which is connected to this intermediate terminal and connected to the first control terminal, amplifies the voltage of the positive half wave of the AC signal and controls the current during the positive half cycle. A first amplification element that is connected to the second control terminal and that amplifies the voltage of the negative half wave of the AC signal and causes current to flow during the negative half cycle period I are connected in parallel to each other. The connected differential amplifier synthesizes the potential fluctuations between the positive half cycle and the negative half cycle of the intermediate terminal connected to the intermediate terminal, and outputs a voltage that fluctuates at twice the frequency of the predetermined frequency. A doubling device that is equipped with a multiplier terminal and outputs a multiplied signal with a frequency twice that of the input AC signal.
JP657382U 1982-01-20 1982-01-20 doubler Pending JPS58109316U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP657382U JPS58109316U (en) 1982-01-20 1982-01-20 doubler

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP657382U JPS58109316U (en) 1982-01-20 1982-01-20 doubler

Publications (1)

Publication Number Publication Date
JPS58109316U true JPS58109316U (en) 1983-07-26

Family

ID=30019361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP657382U Pending JPS58109316U (en) 1982-01-20 1982-01-20 doubler

Country Status (1)

Country Link
JP (1) JPS58109316U (en)

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