JPS58109088U - digital electronic clock - Google Patents
digital electronic clockInfo
- Publication number
- JPS58109088U JPS58109088U JP15918582U JP15918582U JPS58109088U JP S58109088 U JPS58109088 U JP S58109088U JP 15918582 U JP15918582 U JP 15918582U JP 15918582 U JP15918582 U JP 15918582U JP S58109088 U JPS58109088 U JP S58109088U
- Authority
- JP
- Japan
- Prior art keywords
- calculation
- display
- output signal
- digital electronic
- pulse generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electric Clocks (AREA)
- Calculators And Similar Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の実施例を示すブロック図、第2図は本
考案の他の実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention.
Claims (1)
準パルス発生器の出力信号を分周する分周器、障晶や発
光ダイオードなどを用いてディジタル表示を行なう表示
装置および前記表示装置を駆動する表示駆動回路からな
るディジタル電子時計において、入力装置および演算回
路等を含む計算回路からなり、電源スィッチを介して前
記電源に接続された計算機構および時刻情報あるいは前
記計算棒構からの計算情報のいずれを表示するかを選別
する切り替スイッチを備え、前記切り替スイッチと連動
しており、かつ前記計算機構の演算タイミングパルスメ
して前記時間標準パルス発生器 ゛の出力信号もし
くは前記分周器の任意の分周段からの出力信号を用いた
ことを特徴とするディジタル電子時計。Drives a display device that performs digital display using a battery as a power source, a time standard pulse generator, a frequency divider that divides the output signal of the time standard pulse generator, a barrier crystal, a light emitting diode, etc., and the display device. A digital electronic timepiece comprising a display driving circuit, which comprises a calculation circuit including an input device and an arithmetic circuit, and is connected to the power source via a power switch, and a calculation mechanism and time information or calculation information from the calculation stick mechanism. It is provided with a changeover switch for selecting which one to display, and is interlocked with the changeover switch, and uses the calculation timing pulse of the calculation mechanism as the output signal of the time standard pulse generator or any of the frequency divider. A digital electronic clock characterized by using an output signal from a frequency dividing stage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15918582U JPS5932954Y2 (en) | 1982-10-20 | 1982-10-20 | digital electronic clock |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15918582U JPS5932954Y2 (en) | 1982-10-20 | 1982-10-20 | digital electronic clock |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58109088U true JPS58109088U (en) | 1983-07-25 |
JPS5932954Y2 JPS5932954Y2 (en) | 1984-09-14 |
Family
ID=30101904
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15918582U Expired JPS5932954Y2 (en) | 1982-10-20 | 1982-10-20 | digital electronic clock |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5932954Y2 (en) |
-
1982
- 1982-10-20 JP JP15918582U patent/JPS5932954Y2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5932954Y2 (en) | 1984-09-14 |
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