JPS58107670A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To increase a dynamic range, to enhance an S/N ratio, and to make it possible to read a high speed signal in time series by reducing vertical transfer stages with respect to the number of photoelectric transducing elements. CONSTITUTION:Potential wells are formed in a staircase shape or in a slant surface shape and combined with a charge coupling principle. Thus complete transfer mode signal paths, i.e. vertical transfer paths 95-a-95-c, 93-a-93-c, 91-a-91-c and 89-a-89-c are formed. A plurality of photoelectric tranceduer element lines 59-a-87-c are provided in correspondence with pairs of transfer stages. These element lines are sequentially addressed and signal charges are sent to the vertical transfer paths. At this time, the element lines belonging to the neighboring transfer stage in these element lines and the neighboring element lines are simultaneously addressed, and the signal charges are sent to the vertical transfer lines. The signal charges are outputted as a time series signal in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a solid-state imaging device in which a photoelectric conversion element is arranged and formed on a semiconductor substrate.

Technical Background of the Invention - A two-dimensional image sensor (area image sensor) in which photoelectric conversion elements are two-dimensionally arranged on a substrate is particularly useful as an imaging member for a television camera. Figure 1 shows a schematic plan view of such a conventional line address type two-dimensional solid-state imager, and Figure 2 (,) (b) shows the charge transfer from the p-m photodiode vertically through the line number 1. A schematic cross-sectional diagram leading to the device and a potential diagram of each part are shown.

In Figure 81, the first photodiode row (1-1) to (
/-f), second photodiode row (j-1) to (舊-f), eighth photodiode row (J-a) to (a-
ty, fourth photodiode row (4-a) to (4-f
) and the fifth photodiode row (, li -a ) ~
(j-f) are provided in a matrix. In order to transfer signals photoelectrically converted by these photodiodes to vertical signal lines, first to @5 line address gates (6-a)-(
S-f), (7-a)” (7-t), (s-a) ~(
a-r).

(t-a) ~ (91-f), (161-a) ~
The first to fifth address lines are connected via (1θ)−f). A line address scanning circuit block I is connected to the first to fifth address lines in order to sequentially supply transfer pulses to the first to fifth address gates, and the signal charges transferred to the vertical signal lines are paralleled line by line. A horizontal charge transfer device 12 for sequentially serially transferring the charges toward the output circuit 13 is connected to each of them.

In FIG. 2(1), a semiconductor substrate, for example, a P-type semiconductor substrate K, has an impurity layer 14 forming a p-n photodiode, a line address gate 15, and an n-type semiconductor substrate forming a vertical signal line.
A parallel transfer gate (parallel transfer gate) 77 in which a +-type conductive layer 16 is provided and a signal is transferred from this vertical signal line to the charge transfer device 12
A charge transfer device 120, a transfer electrode 18, and a buried channel impurity JJJ9 are formed through the charge transfer device 120. Further, a channel stop 20 made of a P+ type impurity layer is formed along the buried channel impurity layer 19.

In FIG. 2(b), residual carriers 21, signal carriers 22, p of the impurity conductive layer 16 forming the vertical signal 1IiI
-*7 Residual carriers 23 existing in the three layers 14 of the photodiode, potential 24 under the line address gate,
The principle of operation is as shown in the potential 25 below the parallel transfer gate 17 and the channel potential 26f of the charge transfer device. First, a transfer pulse is applied to the first line address gate to transfer the signal charge of the first photodiode column to each vertical signal line. The charges are then transferred in parallel to the horizontal charge transfer device 12 via the parallel transfer gate.

After that, by operating the charge transfer device 12,
$17 The signals of each photodiode in the photodiode array are taken out as time-series signals from the output circuit 13. Hereinafter, all the signals are taken out by applying a transfer pulse to the first line address gate filter using the same operation. I can do it.

Problems of the Background Art The nine conventional line address type two-dimensional sensors described above have the following essential drawbacks.

That is, as shown in the cross-sectional schematic diagram in Figure 2, the capacitance of the vertical signal line is extremely large compared to the amount of signal charge generated and accumulated in the p-type photodiode. The potential fluctuation of the vertical signal line is extremely small when
Moreover, the transfer form when transferring a signal from the impurity layer 16 forming the -direct signal line to the buried channel impurity layer 19 is as follows.
This is a well-known BBD mode, which is a so-called incomplete transfer mode. Therefore, the time it takes for signal charges to be transferred to the charge transfer device is extremely long, and even if the time is lengthened, the amount of transfer increases over time, making it impossible to significantly improve the 8/N ratio. Furthermore, thermal carrier emission occurs from the remaining carriers 21 of the vertical signal line toward the channel potential 26 of the charge transfer device, making it difficult to transfer an accurate amount of signal charge to the charge transfer device. In addition, the variation in the characteristics of each vertical signal line is output as a noise component, and it is difficult to prevent this.

As described above, conventional solid-state imaging devices have several effective methods for reading out signals, but each method has drawbacks that are difficult to avoid.

For example, in an interline transfer type COD image sensor, a CCD is formed in a narrow area between photoelectric conversion elements to transfer signals, so there is a limit to the amount of signal charge, making it difficult to obtain a large dynamic range. ＜ , and a false signal (
In line address type sensors, a large dynamic range can be obtained as shown in the conventional example, but the capacitance of the vertical signal line is 0!
1. Because the signal charge is small. S/N is low and voltage liquid all/
Easily causes I (lL).

Purpose of the Invention The present invention has been made in view of the above-mentioned problems.
It is an object of the present invention to provide a solid-state imaging device that overcomes the drawbacks caused by the incomplete transfer mode due to D-transfer, has a high S/N ratio, and can realize high-speed signal readout.

SUMMARY OF THE INVENTION The present invention combines nine potential wells formed in a stepped or sloped shape and the charge coupling principle to form an all-optical transfer mode (COD mode) signal path, and also forms a plurality of signal paths corresponding to one set of transfer stages. A light 11t conversion element array is arranged, and these light 1
When m conversion element rows are sequentially addressed and signal charges are sent to the vertical transfer path, the photoelectric conversion element rows belonging to adjacent transfer stages among these photoelectric conversion element rows and the adjacent photoelectric conversion element rows are By simultaneously addressing the signal charges and sending them to the vertical transfer path, the signal charges are obtained as time-series signals. In the present invention, the number of vertical '1 transfer stages is reduced relative to the number of light@conversion elements (7), and the two-dimensional solid-state imaging #: 11 has a structure in which the transfer capacity (dynamic range) of each transfer stage is cooled. It operates with simple drive pulses and is characterized by the fact that the generated signal can be sent out as a time-series signal in the same way as the conventional intertransfer method.

Embodiment of the Invention FIG. 8 is a schematic plan view of a solid-state imaging device in which photoelectric conversion elements are arranged two-dimensionally in the column and row directions on a semiconductor substrate. A first photoelectric conversion element array composed of diodes and the like, 29-a to 29-, 3F1 to 33-, etc.
34-a to 34-e are provided between the rows of these optical conversion elements, and these photoelectric conversion elements are
.

Vertical transfer electrodes 35 are vertical transfer electrodes 34-a for transferring signal charges generated in the element rows in parallel in the vertical direction.
1 child, S applying vertical transfer pulse φVlt to ~34-・
6 is a terminal for applying a vertical transfer pulse φ■2 to these vertical transfer electrodes 34a to 34. Terminals 37 to 40 generate line address pulses for sequentially addressing each of the above element columns and transferring signals to the vertical transfer path. Terminals 41 for applying address pulses ~A- from a line address scanning circuit (not shown) to the address gates of each column are transferred in parallel by the vertical transfer electrodes 34-a=J4-. A transfer control electrode receives the signal and transfers it to a horizontal transfer register 42, which will be described later, using a transfer control pulse φ8H.

4JII'i A horizontal transfer register for horizontally sequentially transferring the signals transferred in parallel. 43 is an output circuit that detects the signal charge sent from the horizontal transfer register 42 and takes it out to the outside.

IJ48 diagram (b) shows a cross-sectional structure along the Y-Y edge of Figure 8 (1), where 44 is a horizontal transfer electrode to which horizontal transfer pulse φH1 is applied, 45 is a P-type semiconductor substrate, and 46 is a transfer electrode. A low concentration P type impurity layer 47 which acts as a channel and has the opposite conductivity type as the substrate 45 acts as a transfer channel and has the same conductivity type as the substrate 45;
0.51 is a self-image transfer electrode to which the transfer pulse φv1 is applied; 49. El, 53 is the transfer pulse φV! is the applied vertical transfer t@.

IR8 diagrams (c) to (1) are time 1. of the time chart described later. In the diagram showing the potential distribution formed in ~tvK transfer channels 46 and 47, 54 is the signal charge flux photoelectrically converted by the photoelectric conversion element 2 to 1, and similarly 55 to 58
are the photoelectric conversion elements 29-e, 80-*, and 31, respectively.
-@j3j! -e is the signal charge flux photoelectrically converted.

Next, the operation of the apparatus shown in FIG. 8 will be explained with reference to the time chart of various signal pulses shown in FIG. Each of the photoelectric conversion elements 21B-a to 21B-aj! The signal charge generated at -@ is accumulated in each photoelectric conversion element. After a certain period of time, at time ts, the terminal J7 is output from the line address scanning circuit.
A first column address pulse A1 is applied to the address gate of the first element column through
The signal charges of are transferred to the respective vertical registers.

Before this transfer, in the cross-sectional potential along the Y-Y line in Figure #I8 (Hata), the transfer pulses φVly and φv2 are both at a high level, so the potential well under the transfer electrodes 48 to 53 is deep.
The signal charge 54 from the photoelectric conversion element 28-c is transferred to the bottom of the transfer electrode 4a (see FIG. 8G). When snow falls at time 0, the transfer pulse φVl becomes a low level and the potential below the vertical transfer electrode 48 decreases. The well becomes shallow, and in this state, the phase shift control pulse φ8H becomes a high potential and the phase shift control electrode 4
1. When the potential well below becomes deeper.

The charge flux 54 under the duty transfer electrode 48 is shown in FIG. 8(d).
The data is transferred to the horizontal transfer register 42 as shown at 4C. Thereafter, the transfer and transfer of columns 2 to @6 are performed in the same manner. That is, time 1. , through terminal 3at, -cKz
When the address pulse A1,1 of the column #r8 is applied, the charge flux 55.56 of the column #2, @8 is shown in the ga diagram (@
) as shown in ljI[4 in register J4-@! Then, at time t4, ! Figure 88 Jf)
As shown in FIG. 3, only the charge bundle 55 in the second column is transferred to the next stage. Further, at time 1=, the charge flux 5 of the second column is transferred by the control pulse φεH as shown in FIG.
5 is transferred to the horizontal register 42, and the charge flux s6 is transferred to the next stage.At time t-, the 4th. The address pulse 41 of the fifth column is applied to the address gates of the #c4 column and the stripe 5 column via the terminal s9, and the charge flux s of the fourth column and the fifth column
r and sa are simultaneously transferred to the vertical registers, respectively, as shown in FIG. 8(b). Another hour t! In this case, charge fluxes 57 and 58 are transferred to the next stage as shown in FIG. 8(1). In this way, the signal charge flux of each column is read out from the output circuit 43 in time series via the horizontal transfer register 42. Note that, as shown in FIG. 4, the scanning frequency of the address pulse (A□~M) and the transfer pulse φ
φ■mouse is equal to the frequency of the transfer control pulse φ8H.

In the above embodiment, a pair of transfer electrodes are formed corresponding to two photoelectric conversion elements in the vertical direction, so the number of charge transfer stages is reduced to 1/2 compared to the above-mentioned interline transfer 1111 structure. . Since the number of transfer electrodes is 1/2 in this way, the area of the transfer electrode is doubled in the vertical direction for the same channel width, which means that the vertical register's range (charge transfer capacity It) is 2. increase twice.

FIG. 5 is a diagram illustrating a planar configuration of a two-dimensional solid-state imaging device according to another embodiment of the present invention.
-eiltm'l photoelectric conversion element array, similarly 60-a to 6
0-6.・・Mountain・, 87-a to 81-1 are 2nd to 20th
This is a photoelectric conversion element array. tta, 8to 1~8 Ji -e
Id 4th stage oo-a~5l-cFi 8th stage vertical storage and transfer electrode, 9F1~92-eFi 2nd stage vertical storage and transfer electrode.

94-a to 94-cij first stage vertical storage and transfer electrodes, 89
-a to 89- are W44-stage vertical transfer paths consisting of a plurality of electrodes to which different constant bias voltages are applied, similarly K 9
J-a~9 1-c lam 8-stage vertical transfer path, 93
-a to 93-c are second stage duty transfer paths, 911 to 95-c
is the first branch vertical transfer path, and 96 is the vertical storage transfer pulse φV.
97 is a transfer control electrode for transferring the vertically transferred electric charge to the horizontal transfer register by transfer control pulse φ5iijc, 98IIi is a horizontal transfer register for transferring the electric charge to the output circuit, 99 to 118 are terminals for applying . 1st to 20th addresses for transferring the charges obtained in the first photoelectric conversion element rows 59-a to 59-c to the 20th photoelectric conversion element rows 95-a to 95-c to the corresponding vertical transfer paths It is a gate. In this case, the fifth. Comrade 6th Address Gate,
10th. Comrade Ill Address Gate, 15th. The 16th address gates are commonly connected. Then, corresponding to each of the above address gates, address pulses 1-
is applied. These address pulses A~m,
・The timing of the transfer pulse φv1 and the transfer control pulse φ8H is shown in Figure 6.

Fig. 7 (a) n @ Fig. 5 In Fig. 0 showing the cross-sectional structure along the oz-zm, 124 to 121 are the fourth stage vertical transfer paths 89-e f, and different constant voltages are applied to each. An insulating layer 11 is formed on the substrate 45 by vertical transfer electrodes.
J Jl is arranged via x.

Similarly, KJjJ~181 constitutes the second stage vertical transfer path 91-. Vertical transfer electrodes to which different constant voltages are applied,
132 to 135 constitute the second stage vertical transfer path 9 J − *, and vertical transfer electrodes to which different constant voltages are applied, respectively;
736 to 139 constitute a second stage vertical transfer path 95-@,
Vertical transfer electrodes 140 to which different constant voltages are applied
are first to fourth stage vertical transfer paths #9-t, 91-@, 93-
@.

95-e electrically isolated independent electrodes 124-1
This is a pressure dividing resistor element for dividing the voltage of the power supply 141 in order to supply the necessary DC voltage to B9. Other parts that are the same as those in FIG. 8(b) are given the same reference numerals.

FIGS. 7(b) to (h) show the tying time 1=1 in FIG. 6. A potential distribution diagram of the vertical transfer channel at . LB6. LaI
3. LaI4゜L875. LaI3. LaI7 is a photoelectric conversion element '12-*, 73-c, 80-, respectively.
a, 81-a, 82-a.

These are the signal charge fluxes obtained in 8B-a and 84-a.

Next, in the case of the above-mentioned other embodiments, the movement in 2.7
Explain the work. The address pulses A1 to A3 in FIG. 6 correspond to the first to 20th address gates 99 to 118 in FIG. 5, respectively. is applied.

Therefore, at one time t=tl, address pulse 1 is applied to the I11 address gate 99, and the signal charge flux LS1 obtained in the photoelectric conversion element arrays 59-a to 59-@ is transferred to the fourth stage vertical storage and transfer path 89. - forwarded to C. The potential distribution in the vertical transfer channel at this time is shown in FIG. 7(b) At time 0=ts, the charge flux LBI is transferred to the horizontal "transfer register 98" by the transfer ff11111 pulse φ8H as shown in FIG. 7(e). Thereafter, address pulses A, -M are applied to the second to fourth address gates, and the addressed signal charges are sequentially transferred to the horizontal transfer register 98 in the same manner as above at time ts. In,
Fifth. 6 address gate is address pulse A le
The signal charge flux L85 of the 5th and 6th dark blue columns is simultaneously addressed by . Of L86, charge flux LB5 is transferred to the fourth stage vertical transfer w! At t89-, the charge flux L86 is transferred below the eighth stage vertical storage and transfer electrode, resulting in a potential distribution as shown in FIG. 7(d). Furthermore, at time t=t4, signal charge flux L95
°L86 is transferred to the next stage by the transfer operation as shown in FIG. 7(-)K. Similarly, after address designation is performed by applying address pulses ``mm'' to the 7th to 9th address gates, @10. [11 Address gate is hot with address pulse. , ■ and further @
The 12th to 14th address gates are address pulses A11 to
After being addressed by the A duplex number, time 1=1. When it comes to the 15th. The 16th address gate is the address pulse A1
Addressed by 1sl@. This situation is shown in Fig. 7(f), and 1! ! 4th to I41 vertical storage transfer electrodes 8B-e, 90-@, 92-@.

94-@ Below are photoelectric conversion elements 80-a and 81-a in the 18th, 14th, and 15th columns, respectively.

a! -*, signal charge flux L813~L obtained in 83-a
At time 0 1=1 when SJ6 exists, these signal charge fluxes are transferred to the next stage as shown in FIG. -a signal charge flux L817 is transferred.

The potential distribution within the transfer channel at this time is shown in FIG. 7(h).

The gIi charge fluxes obtained by each photoelectric conversion element in this manner can all be sent out as time-series signals. Moreover, in the case of this embodiment, in which the necessary pulses are only simple synchronous pulses as shown in FIG. 6, one vertical storage electrode corresponds to five vertical photoelectric conversion elements, lil& which has a plurality of electrodes to which different DC voltages are applied.
One of its characteristics is that it has a structure in which vertical transfer paths exist. In other words, the size of the vertical storage and transfer electrode responsible for storage and transfer of charge can be freely adjusted over several photoelectric conversion elements. Therefore, the transfer capacity of the vertical transfer means can be increased several times, and the dynamic range of the element can be increased several times compared to the interline transfer method. Note that the address pulses are: 1. .

Al11*11em1. ．． Although two pulses as in 1. are inappropriate, it goes without saying that one pulse is sufficient.

The present invention can be implemented in various ways without being limited to the above-mentioned embodiments6. For example, by using a resistive electrode as a vertical transfer path electrode or by controlling the thickness of an insulating film, the channel potential can be made sloped rather than stepwise. The number of photoelectric conversion elements provided corresponding to the charge transfer electrodes 1411 may be any number.

Effects of the Invention According to the solid-state imaging device of the present invention, since the number of vertical transfer stages is reduced relative to the number of photoelectric conversion elements, the dynamic range is increased, the %S/N ratio is high, and signals can be read out at high speed in time series. can form fruit blocks.

[Brief explanation of the drawing]

The first is a schematic plan view showing a conventional line address type two-dimensional solid-state imager, and the stripe diagrams (a) and (b) are X-X in Figure @1.
FIG. 8(a) is a schematic plan view of a two-dimensional solid-state imaging device according to the @l embodiment of the present invention, and FIG. 8(b) is a sectional view along +16iFC and its botential diagram. To knee Y#? E), Yu. ,. ', 481°, 1~
(1) is the botential diagram of Figure 8(b), and broom 4, respectively.
The figure is a timing pulse diagram for explaining the operation of Figure #I8, Figure 5 is a schematic plan view of a two-dimensional solid-state imaging device according to the second embodiment of the present invention, and Figure 6 is a diagram of the device of Figure 5. A timing pulse diagram for explaining the operation, FIG. 7(a) is a cross-sectional diagram of $111 along the z-2 line in FIG. 5, @7(b) to (
h) Figure 147 (,) is the potential n/diagram. 28-a~3 B-*, S9-a~87-c
...Optical 4-diverting element array, 34-a to 34-., aa-@
~94-e... Vertical storage transfer electrode, 41.97...
・Transfer control electrode, 42,911...Horizontal transfer register, 44...Horizontal transfer electrode, 45...Semiconductor substrate, 4
6゜47... impurity layer, 4B, 53,124~13g
・*Direct transfer electrode, 54-58. Ls1~Ls17...
Eccentric load bundle, 89-a to 95-c...Vertical transfer 4.9
9-115...Address Key), A1 Hem. ...address pulse, φ8H...transfer control pulse. φV1+φV! ...Transfer control pulse, φH! ,φ■v
・・Horizontal transfer pulse dispatcher person Patent attorney Takehiko Suzue Figure 1 d d ”
ζt s41! Il Figure 5

Claims (1)

[Scope of Claims] (1) A photoelectric conversion element arranged in a Madrisk pattern on a substrate and generating a signal charge according to the incident intensity; Vertical transfer of the signal charges transferred in parallel by the direct transmission means; horizontal transfer means for horizontally transferring the signal charges transferred in parallel by the vertical transfer means; The output (b) path that is taken out sequentially! , when at least 42 or more photoelectric conversion element rows are arranged and the photoelectric conversion element rows are sequentially addressed to transfer signal charges to the vertical transfer means, adjacent transfers among the photoelectric conversion element rows are arranged. What is claimed is: 1. A solid-state imaging device comprising a photoelectric conversion element array belonging to a stage and adjacent photoelectric conversion element arrays that simultaneously transmit signal charges to the vertical transfer means. (2) Address gates corresponding to each of the photoelectric conversion elements FcFi are provided, and the address gates of the adjacent photoelectric conversion element arrays to be addressed simultaneously are connected in common and driven by the same address pulse. The solid-state imaging device according to claim 1, wherein fl: % mold. (8) Claims 1 and 2, characterized in that one address pulse is applied to one row of address gates each time the signal charge flux existing in the vertical transfer stage is transferred one stage. The solid-state imaging device according to any one of the following. (4) address scanning frequency of the address pulse;
Claim 1, characterized in that the frequency of the vertical transfer pulse for driving the vertical transfer stage and the frequency of the transfer control pulse for phase shifting the signal charge from the vertical transfer means to the horizontal transfer means are the same frequency. The rigidity described in any of paragraphs 8 to 8