JPS58106883A - Manufacture of composite substrate - Google Patents

Manufacture of composite substrate

Info

Publication number
JPS58106883A
JPS58106883A JP56205644A JP20564481A JPS58106883A JP S58106883 A JPS58106883 A JP S58106883A JP 56205644 A JP56205644 A JP 56205644A JP 20564481 A JP20564481 A JP 20564481A JP S58106883 A JPS58106883 A JP S58106883A
Authority
JP
Japan
Prior art keywords
substrate
wafer
semiconductor material
thin film
height gauge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56205644A
Other languages
Japanese (ja)
Other versions
JPS638636B2 (en
Inventor
Tetsuo Sekiya
哲夫 関谷
Hideo Suyama
英夫 陶山
Toshiaki Wada
和田 俊朗
Yoshiaki Katsuyama
勝山 義昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Proterial Ltd
Original Assignee
Sony Corp
Sumitomo Special Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, Sumitomo Special Metals Co Ltd filed Critical Sony Corp
Priority to JP56205644A priority Critical patent/JPS58106883A/en
Publication of JPS58106883A publication Critical patent/JPS58106883A/en
Publication of JPS638636B2 publication Critical patent/JPS638636B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00Hall-effect devices

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Hall/Mr Elements (AREA)

Abstract

PURPOSE:To obtain electron mobility equal to a bulk material by a method wherein a soft magnetic material substrate is formed in size larger than a semiconductor material wafer, the wafer is fixed, the outer circumference of the substrate is coated with a height gage consisting of a hard ceramic material and the upper surface of the gage is mechano-chemical-polished while being used as a reference surface. CONSTITUTION:Mechano-chemical polishing is executed onto one surface of the Nn-Zn ferrite substrate 1, and the polished surface P1 is coated with an insulating thin-film layer 2 made of Al2O3, etc. Mechano-chemical polishing is executed onto the surface of the semiconductor material wafer 3, which is made of InSb and size thereof is smaller than the ferrite substrate 1, and the polished surface P2 is joined with the surface of the insulating thin-film layer 2 by using an adhesive material 4. The ring-shaped height gage 5 composed of the hard ceramic material made of Al2O3, etc. is attached to the cicumferential section 10 of the outer end of the ferrite substrate 1. The gage is attached in consideration of the thickness of the insylating layer 2, the thickness of the adhesive material 4, the thickness of the wafer and the finishing thickness size of the substrate at that time. The wafer 3 is processed while using the upper surface of the gage as a reference, and a polished surface P3 is formed.

Description

【発明の詳細な説明】 この発明は、ホール素子の製造において用いられる複合
基板を、磁性材料基板並びに半導体材料ウェハーの表面
をメカノケ【カル・ポリッシングによりほぼ完全結昌吠
態に保持して製造する方法に係り、メカノケミカル・ポ
リッシングによる半導体材料ウェハーの最終精密仕上げ
を能率よくかつ高精度84行なう複合基板の製造方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention manufactures a composite substrate used in the manufacture of Hall elements by maintaining the surfaces of a magnetic material substrate and a semiconductor material wafer in an almost completely formed state by mechanical polishing. The present invention relates to a method for manufacturing a composite substrate in which the final precision finishing of a semiconductor material wafer is efficiently and precisely performed by mechanochemical polishing.

一般に、ホール素子の製造方法としていわゆるバルク法
と呼ばれる製法があり、ξれは所定の軟質磁性材料基板
上にIn5be GIIAI等の金属間化合物半導体材
料ウェハーを接着し、この半導体材料ウニ、バーを所定
の厚みまで機械研摩あるいは化学研摩によって加工した
複合バルク基板を用いる製法である。
In general, there is a manufacturing method called the so-called bulk method as a manufacturing method for Hall elements, in which a wafer of an intermetallic compound semiconductor material such as In5be GIIAI is bonded onto a predetermined soft magnetic material substrate, and this semiconductor material urchin and bar are bonded to a predetermined soft magnetic material substrate. This manufacturing method uses a composite bulk substrate processed by mechanical or chemical polishing to a thickness of .

この際、磁性材料基板はその表面がダイヤモンド粉その
他の砥粒で研摩されているため、その表面層に加工流動
層、変形変質層あるいは応力残潅層が存在し、そめ′後
の工程において上記応力や歪により悪影響を及ぼしてい
る。また半導体材料ウェハーの場合も同様に悪影響があ
り、例えばIflSb膜の電子移動度がバルク材特性よ
り低く十分なるSA比を得ることができなかった。
At this time, since the surface of the magnetic material substrate is polished with diamond powder or other abrasive grains, a processed fluidized layer, a deformed altered layer, or a stress residual layer is present on the surface layer, and in the process after polishing, the above-mentioned It is adversely affected by stress and strain. Further, in the case of semiconductor material wafers, there is a similar adverse effect; for example, the electron mobility of the IflSb film is lower than the bulk material characteristics, making it impossible to obtain a sufficient SA ratio.

そこでこの発明は、基板の表面層に変質層が生じないよ
うに、超精密なメカノケミカル・ボリア’j!eより表
面仕上げを行ない、tた半導体材料も同様にウェハー画
面を順次メカノケミカル・ポリVし轟することにより、
各表面をほぼ完全結晶吠態に゛保持し、高い電子移動度
を得ている。
Therefore, this invention uses ultra-precise mechanochemical boria to prevent the formation of a degraded layer on the surface layer of the substrate. After finishing the surface of the semiconductor material, the wafer surface is sequentially coated with mechanochemical poly-V in the same way.
Each surface is maintained in an almost perfect crystalline state, resulting in high electron mobility.

ここでメカノケミカル・4すVシンクとは、Sin、 
、ム1ava s MgO等の粒径0.001〜0.0
5μ鱈の超微細粉末を純水中に懸濁させた液を用いて、
被加工材を液中ラップ方式で加工する方法である。
Mechanochemical 4S V sink here means Sin,
, MgO, etc. particle size 0.001-0.0
Using a solution in which ultrafine powder of 5μ cod was suspended in pure water,
This is a method of processing workpiece materials using a submerged lapping method.

すなわち、所定割合とした超微細粉末の純水中懸濁液を
貯めた春器内化、例えば円板型のラップを回転させ、被
加工材を液中にてラップと対向させて相対的に回転させ
、液中加工するものである。
In other words, a suspension of ultra-fine powder in pure water at a predetermined ratio is stored in a spring container, for example, a disk-shaped wrap is rotated, and the workpiece is placed facing the wrap in the liquid and relatively It is rotated and processed in liquid.

うVプ材、ラップ速度は超微細粉末の諺類、粒径や一一
鳳、被加工材等により適宜選定すればよく、純水中の懸
濁量は0.5〜20ft%が好ましい。
The wrapping material and the wrapping speed may be appropriately selected depending on the ultrafine powder, particle size, grain size, material to be processed, etc., and the amount of suspension in pure water is preferably 0.5 to 20 ft%.

とξろで、磁性材料基板に接着したIflSb、GaA
l等の半導体材料ウェハーは、所定厚み例えば2±1μ
−まで加工する必要がある。仁れを上記のメカノケミカ
ル・ブリッジングで行なう場合、特殊な治具を使用して
行なう必要があるため、加工能率に問題を生じる。その
ため加工能率を考慮して、lO±5μ園までメカノケミ
カル・ポリッシングを施し、その後2土1μ鰯までケ藏
カル−エツチングする方法を採るξともできるが、加工
工程が増えるため好ましくない。
IflSb, GaA adhered to the magnetic material substrate with
The semiconductor material wafer, such as l, has a predetermined thickness, for example, 2±1μ.
- It is necessary to process it up to -. When the chamfering is performed using the mechanochemical bridging described above, it is necessary to use a special jig, which causes problems in processing efficiency. Therefore, in consideration of processing efficiency, it is possible to apply mechanochemical polishing to 10±5 μm and then chemical etching to 1 μm of sardine, but this is not preferable because the processing steps increase.

また、最終仕上げまで行なう際に、特殊な治具を使用せ
ずにメカノケ【カル・ポリツシングを施した場合には厚
みにバラツキが生じやす(、高い平坦度を得るのは困難
となる。
Additionally, if mechanical polishing is performed without using a special jig during final finishing, variations in thickness tend to occur (and it is difficult to obtain high flatness).

そ゛こで、さらにこの発明方法では、上記の複合基板を
得る製法において、軟質磁性材料基板を金属間化合物半
導体材料ウェハーより大番い寸法とし、基板上書ζ上記
ウェハーを固着後、基板の外周余白部に、硬質セラtI
Fり材からなる高さゲージを被着し、上記半導体材料ウ
ェハーを高さゲージの上面を基準面としてメカノケミカ
ル・ポリッシングで超精密加工することにより、能率よ
くかつ高精度に仕上げるものである。すなわち上記の方
法で2±0.5μ調まで精密加工することがで伽る。
Therefore, in the method of the present invention, in the manufacturing method for obtaining the above-mentioned composite substrate, the size of the soft magnetic material substrate is larger than that of the intermetallic compound semiconductor material wafer, and after the above-mentioned wafer is fixed, the outer periphery of the substrate is Hard Cera tI on the margins
The semiconductor material wafer is finished efficiently and with high precision by attaching a height gauge made of fluorine material and ultra-precisely processing the semiconductor material wafer using mechanochemical polishing using the upper surface of the height gauge as a reference surface. In other words, the above method allows precision machining up to 2±0.5μ.

次に軟質磁性材料基板には、Mn −Znnフチイ)、
N1−Zfiフェライトなどのソフトフェライト等が使
用できるが、例えばMn −Znフェライトはその固有
電気抵抗が数100=−であるため、例えばIflSb
の半導体材料ウェハーと導電性であるハンダ層を介して
接合する1lIK:絶縁薄膜層を必要とする。一方%N
1−Zllフェライトはその固有電気抵抗がI X 1
0・Ω−゛−以上であるため絶縁薄膜層を介在aする必
要がない、tた、ハンダ層が導電性であるため、半導体
材料ウニへ−側にも同様に絶縁薄膜層を設ける必要があ
る。これらの絶縁薄膜層にはhim 0−1810m 
、5i−N4等の酸化物材料を用いることができる。
Next, for the soft magnetic material substrate, Mn-Znn fuchii),
Soft ferrites such as N1-Zfi ferrite can be used, but for example, Mn-Zn ferrite has a specific electrical resistance of several hundred = -, so for example IflSb
1lIK: Requires an insulating thin film layer to be bonded to the semiconductor material wafer through a conductive solder layer. On the other hand, %N
1-Zll ferrite has a specific electrical resistance of I
Since the solder layer is conductive, it is not necessary to provide an insulating thin film layer on the other side of the semiconductor material. be. These insulating thin film layers include him 0-1810m
, 5i-N4, or the like can be used.

なお、ハンダ層の材料には、ハンダ材の液相線が111
8b%oatsの脆性、蓋性遍移温度を越えない範囲の
ものを選ぶ必要があり、組成としては、重量%で pb
言S11 謬 4B  :  55〜90:10の組成
とする仁とが好ましい。
Note that the solder layer material has a liquidus line of 111
It is necessary to select a material that does not exceed the brittleness and lid transition temperature of 8b% oats, and the composition is PB in weight%.
Word S11 Error 4B: It is preferable to have a composition of 55 to 90:10.

金属間化合物半導体材料ウェハーには、すぐれた電子移
動度が得られるIamb%GIAIが適しており、すぐ
れた特性を得るのに単結晶であることが望ましいが、多
結晶のものであっても、乙の発明による複合基板ではす
ぐれたものが得られる。
Iamb% GIAI is suitable for intermetallic compound semiconductor material wafers because it provides excellent electron mobility, and single crystal is desirable to obtain excellent properties, but even polycrystalline wafers are suitable. An excellent product can be obtained from the composite substrate invented by Party B.

以下にこの発明による複合基板の製造方法を図面曇ζ基
づいて説明する。
The method for manufacturing a composite substrate according to the present invention will be described below with reference to the drawings.

第1図は基板と半導体材料ウニ八−を接着材で接合する
場合の工程図であり、第2図は基板と半導体材料ウェハ
ーとの接合に、それぞれに被着した溶着用のハンダ層を
対向8葉、加熱圧着する場合を示している。
Figure 1 is a process diagram for bonding a substrate and a semiconductor material wafer with an adhesive, and Figure 2 is a process diagram for bonding a substrate and a semiconductor material wafer with a solder layer for welding applied to each. 8 sheets, showing the case of heat and pressure bonding.

まず第1図から説明する。軟質磁性材料にMu−Znフ
ェライトを用いてフェライト基板(11となし、その−
画にメカノケミカル・ぼりツシングを施こしくa図)、
この49191面(Pi)tcAIgoms810m 
−5i−Na等の酸化物の絶縁薄膜層(鵞)を300〜
5oooAの厚みで、スパフターあるいは蒸着により被
着する(b図)。
First, explanation will be given from FIG. A ferrite substrate (11 and its -
The image is mechanochemically applied to the image (Figure a),
This 49191 page (Pi)tcAIgoms810m
-5i-Insulating thin film layer of oxide such as Na (Rose) from 300~
It is deposited to a thickness of 500A by spafter or vapor deposition (Figure b).

次に金属間化合物半導体材料に例えばtfisb。Next, for example, tfisb is added to the intermetallic compound semiconductor material.

QIAl等を用いて、フェライト基板+1)より小寸法
の半導体材料ウェハー(3)の−面にメカノケ【カル・
ポリVレンゲを施乙しく0図)、そのブリッジ1面(R
)を上記のフェライト基板(1)の絶縁薄膜層(1表面
に接着材(4)を用いて接合する(d図)。
Using QIAl, etc., mechanoke [Cal-
The poly V astragalus is shown in Figure 0), and its bridge 1 side (R
) is bonded to the surface of the insulating thin film layer (1) of the ferrite substrate (1) using an adhesive (4) (Figure d).

続いて、半導体材料ウェハー1mlを接着した基板(1
)の伺も被着していない余白部分、例えば、円板型の基
板並びに半導体材料ウェハーを用いた場合はフェライト
基板(1)の外端円周部(至)に、Aj露0@等の硬質
セラlyり材からなるリング状の高さゲージIIlを真
空蒸着あるいは反応蒸着で被着する(0図)、この場合
、高さゲージ1li)は基板(り上の絶縁層(1厚、接
着材(4)層厚、半導体材料ウェハー(3)厚並び檻そ
の仕上げ厚み寸法を考慮して、所定の高さ家で基板(1
)上に被着する。
Next, a substrate (1
), for example, if a disk-shaped substrate or a semiconductor material wafer is used, the outer circumferential portion (toward) of the ferrite substrate (1) is coated with Aj dew 0@, etc. A ring-shaped height gauge IIl made of hard ceramic material is deposited by vacuum evaporation or reactive evaporation (Fig. 0). Material (4) layer thickness, semiconductor material wafer (3) thickness, thickness of substrate (1)
) coated on top.

次に、ξの高さゲージ(11の上面を基準として、メカ
ノケミカル・ブリッジングにより半導体材料ウニ八−(
3)を加工し、高専ゲージf1)高さ家でポリVレンゲ
して最終仕上げポリッシング(P−)とする(f図)。
Next, using the top surface of the height gauge ξ (11) as a reference, the semiconductor material 8-(
3) is processed and poly-V machining is performed using a technical college gauge f1) to obtain the final polishing (P-) (Figure f).

以上の工程を経て得た複合基板は、最終仕上1ブ精度が
±05#111以下でメカノケミカル・ボIJツシング
されているため、極めてすぐれた特性61得られ、表面
の完全結晶性並びにI<ルク材と同等の電子移動度が得
られる。
The composite substrate obtained through the above process is mechanochemically bored IJ with a final finishing accuracy of ±05 #111 or less, so it has extremely excellent properties 61, and has perfect surface crystallinity and I< Electron mobility equivalent to that of aluminum materials can be obtained.

なお、高さゲージは硬質セラ1ツク材を用もするため、
メカノケ(カル・ポリッシングをItしめ他のラッピン
グ等の加工時に、高さゲージ自体の寸法精度が変動する
ことは少な一1力式、加工暑とよる高さゲージの変化を
防止するため、耐摩耗性薄膜を高さゲージの上面に被着
すること修ζより、耐摩耗性を向上させるのもよい、耐
摩耗性薄膜暑ζ4よ、zrOsの酸化物、5iO−Nn
やTINの窒化物、Tie sWC%Sl(:の炭化物
の材料を使用すること力喀でaる。
In addition, since the height gauge also uses hard ceramic material,
The dimensional accuracy of the height gauge itself is unlikely to fluctuate when polishing is applied and other processes such as lapping are applied. It is also good to apply a thin film on the top surface of the height gauge to improve wear resistance.
It is preferable to use materials such as nitride of TIN, carbide of Tie sWC%Sl(:).

続いて第2図に基づいて説明する。Next, explanation will be given based on FIG. 2.

軟質磁性材料にM!l −Znフェライトを用−Aて円
板型のフェライト基板11)となし、その−面層ζメカ
ノケ電カル・ポリッシングを施ζしく1図)、このポリ
vLIah面(P、)にkbO−等の酸化物の絶縁薄膜
層(幻を300〜5oooAの厚みで、ス/(ツタ−あ
るいは蒸着により被着させる(b図)。続(1て絶縁層
(り上に溶着用の/1ンダ材例えIf To : Sn
m45−10 ! 51S 〜10(7)組成をX /
f vターある−1は蒸着により被着し、例えば5oo
A厚みの/Xンダ層(・)とする(0図)。
M for soft magnetic materials! A disk-shaped ferrite substrate 11) is made of l-Zn ferrite, and its -face layer ζ is subjected to mechanical electropolishing (Fig. 1), and this polyvLIah face (P, ) is coated with kbO-, etc. An insulating thin film layer (illustration) of oxide is deposited with a thickness of 300 to 500A by sintering or vapor deposition (Figure b). Example If To: Sn
m45-10! 51S ~10(7) composition as X/
f vter -1 is deposited by vapor deposition, for example 5oo
Let it be a /X layer (・) with a thickness of A (Figure 0).

次に、金属間化合物半導体材料に1flSbを用−1、
基板(1)よ−り小径の円板型となした、半導体ウエノ
λ−1m1の一面にメカノケミカル・ポリッシングを施
こしくd図)、乙の半導体材料ウニ/N −+$1のボ
1)ツシー面(P8)上にkhOl等の酸化物の絶縁薄
膜層())を例えば300〜3000大の厚みでスノ(
ツタ−あるいは蒸着によ−被着すa(0図)。続tl′
%てこの絶縁層(マ)上に溶着用の7Xンダ材゛を上記
と同様暑と被着してSOOλ厚みの11ンダ履1m1)
とする(f図)。
Next, using 1 flSb as an intermetallic compound semiconductor material,
Mechanochemical polishing is applied to one side of the semiconductor wafer λ-1m1, which has a disk shape with a smaller diameter than the substrate (1) (Fig. d), and the semiconductor material wafer 1/N-+$1 ) An insulating thin film layer ()) of oxide such as khOl is coated on the surface (P8) with a thickness of 300 to 3000 mm.
Deposited by ivy or vapor deposition (Figure 0). Continued tl'
% Apply 7X solder material for welding on the insulating layer (Ma) of the lever in the same way as above, and make 11x solder material with SOOλ thickness (1 m1).
(Figure f).

そして、フェライト基板+1)と半導体材料ウエノ1−
(S)のハンダ層(・)(I)を対向させて、例え−f
230〜2!!O’011度で加熱圧着して両者を接合
する(g図)。
Then, the ferrite substrate +1) and the semiconductor material Ueno1-
For example, -f
230~2! ! The two are bonded together by heating and pressure bonding at 0'011 degrees (Figure g).

次にフェライト基板(1)の余白部たる外側円周部Oα
に半導体材料ウェハー(3)の厚み並びに仕上寸法、絶
縁薄膜層1?> Illの厚み、ハンダ層(@l+81
の厚みを考慮して、M、O,等の硬質セラ(ツク材から
なるリング状の高さゲージ(−)を真空蒸着あるいは反
応蒸着で被着し、このゲージ+11面を基準として、メ
カノケミカル・ポリッシングにより半導体材料ウェハー
(3)を加工し、高さゲージ(9)高さまでこれをポリ
ッシングして最終仕上げポリッシング(P−)とする(
h図)。
Next, the outer circumference Oα which is the margin of the ferrite substrate (1)
What are the thickness and finished dimensions of the semiconductor material wafer (3) and the insulating thin film layer 1? > Thickness of Ill, solder layer (@l+81
A ring-shaped height gauge (-) made of hard ceramic such as M, O, etc. is deposited by vacuum evaporation or reactive evaporation, taking into consideration the thickness of the mechanochemical・Process the semiconductor material wafer (3) by polishing and polish it to the height of the height gauge (9) for final polishing (P-) (
h figure).

以上の第2図の工程を経て得られた複合基板は、フェラ
イト基板(1)と半導体材料ウェハー(3)との接合に
それぞれに被着したハンダ層で溶着しているため、上記
例の場合0.17111の薄く均一でかつ強度の安定し
た接着層となり、半導体材料ウェハーII)の平坦度が
良くなっており、最終成上げ精度も±0.5#群でメカ
ノケミカル・ポリッシ、されているため、極めてすぐれ
た特性が得られ、表面の完全結晶性並びにバルク材と同
等の電子移動度が得られる。
In the composite substrate obtained through the process shown in Fig. 2 above, the ferrite substrate (1) and the semiconductor material wafer (3) are welded together with the solder layer deposited on each, so in the case of the above example, The adhesive layer is thin, uniform, and has stable strength of 0.17111, and the flatness of the semiconductor material wafer II) is improved, and the final finishing accuracy is mechanochemically polished to ±0.5# group. Therefore, extremely excellent properties can be obtained, with perfect surface crystallinity and electron mobility equivalent to that of bulk materials.

以下にこの発明による実施例を説明する。Examples according to the present invention will be described below.

実施条件 (支)基板(1)−一高書度Mn −Znフェライト3
5φ×3麿形状、 (ロ) 絶縁層(創(yl + −Ar108を100
0λ厚みに蒸着、Q→ ハンダ層+@1lI)−−50
0λ厚みにスパッタリング、 層組成−−Pb : Sn菖62 : 3gスバシター
条件−一・パワー+ 100W/4“φAr圧13〜6
X10−”torr 電極間距離+35m サンプル温度+ R,T〜 50℃ ゲージy)+Pb:811 冨50 :50 、X/fpターレイト+400λ/mlnに) 半導体
ウェハー園−・−7nsb、 25φX0.2m(ホ)
 メカノケミカル・It 17 wシング・・・−純水
中一一液一粒径釦■μ簿、Slα、0.5〜2OWt紙
ラップ適度−40〜6oI11/m1n加工時間・・・
15〜3Qmln。
Implementation conditions (support) Substrate (1) - High-grade Mn-Zn ferrite 3
5φ x 3mm shape, (b) Insulating layer (wound (yl
Vapor deposited to 0λ thickness, Q → solder layer + @1lI) --50
Sputtering to a thickness of 0λ, layer composition--Pb: Sn iris 62: 3g Subacitor conditions--1.Power + 100W/4"φAr pressure 13~6
X10-"torr Inter-electrode distance +35m Sample temperature + R, T ~ 50℃ Gauge y) + Pb: 811, depth 50:50, )
Mechanochemical・It 17 w Sing...-Pure water, one liquid, one particle size button ■μ book, Slα, 0.5~2OWt Paper wrap Moderate -40~6oI11/m1n Processing time...
15-3Qmln.

(へ) 接着材+41・・・・・低粘度樹鮨系ボンド、
3000λ厚み、 (0ハンダ層1@l illの溶着−・−・恒温炉にて
治具を用い、300 f/ctlの圧力でピストン方式
で加熱圧接、温度240°C1 以上の条件で上述したこの発明による2種の製造方法で
゛複合基板を作製し、フェライト基板+11の外側円周
部(11に、2〜3W幅のリング状高さゲージ1lil
 tallを真空蒸着し、接合に接着材(4)を用いる
場合(第1図、0図)には、高さゲージ(6)の高さは
2.4μ調の高さで、又、ハンダ層(@l、(@1を溶
着する場合(第2図り図)には、高さゲージ(9)は2
.3m層の高さで被着した。
(to) Adhesive material +41...Low viscosity wood-based bond,
3000λ thickness, (0 solder layer 1@ill welding) - Using a jig in a constant temperature furnace, heat pressure welding with a piston method at a pressure of 300 f/ctl, and at a temperature of 240°C or higher. A ``composite substrate'' was produced using two manufacturing methods according to the invention, and a ring-shaped height gauge of 2 to 3 W width 1 liter was attached to the outer circumference of the ferrite substrate + 11 (11).
When the solder layer is vacuum-deposited and the adhesive (4) is used for bonding (Figures 1 and 0), the height of the height gauge (6) is 2.4μ, and the solder layer is (@l, (When welding @1 (second diagram), the height gauge (9) is 2
.. A layer height of 3 m was deposited.

高さゲージ1et) (Illを被着したのち、メカノ
ケミカル・ポリッシングにより最終仕上げを行なったと
ころ、接着材(4)を用いた製造方法の場合、半導体材
114ウエハー(3)の厚みは2±0.5μ調の精度で
仕上を完了した。又、ハンダ層+6+、 ’+11を用
いた製造方法の場合は、2±0.4μ簿の精度で半導体
材料ウニ八−(組を請書仕上げする仁とができた。さら
に、表面は完全結晶性を保持しており、表面粗さは±2
0λであり、バルク材と同等の電子移動度が得られた。
(Height gauge 1et) (After applying Ill, the final finishing was performed by mechanochemical polishing. In the case of the manufacturing method using the adhesive (4), the thickness of the semiconductor material 114 wafer (3) was 2± Finishing was completed with an accuracy of 0.5μ.In addition, in the case of the manufacturing method using solder layers +6+ and '+11, the finishing was completed with an accuracy of 2±0.4μ. Moreover, the surface maintains perfect crystallinity, and the surface roughness is ±2.
0λ, and an electron mobility equivalent to that of the bulk material was obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図はこの発明による複合基板の製造方法を
説明する工程図であり、111141図は基板と半導体
材料ウェハーとの接合に接着材を用いる場合、第2図は
同じ(接合にハンダ材を用いる場合である。 図中 1一基板、2,7−絶縁層1[JLI−半導体材
料ウニへ−14−接着材、5.9・−高さゲージ、6.
8−ハンダ層、P、、Pt、P、−49191面、l〇
−外側円周部。 出願人 ソニー株式会社 同   住友特殊金属株式会社 〈1 代理人  押  1) 良 第1図 (α) =浴]+ (b)二二二り〒 (C)  ラ「ゴー3
1 and 2 are process diagrams explaining the method for manufacturing a composite substrate according to the present invention. This is a case where solder material is used. In the figure: 1 - substrate, 2, 7 - insulating layer 1 [JLI - to semiconductor material - 14 - adhesive, 5.9 - height gauge, 6.
8-Solder layer, P,, Pt, P, -49191 plane, l〇-outer circumference. Applicant Sony Corporation Sumitomo Special Metals Co., Ltd. 1 Agent 1) Ryo Figure 1 (α) = Bath] + (b) 222 〒 (C) Ra “Go 3”

Claims (1)

【特許請求の範囲】 l メカノケミカル・ブリッジングにより超精密仕上げ
を行なった軟質磁性材料基板の表面に必要により絶縁薄
膜層を被着し、次に上記基板寸法より小なる金属開化合
物半導体材料ウェハーの一画をメカノケミカル・ポリッ
シングにより超精密仕上げを行ない、上記絶縁薄膜層を
被着した軟質磁性材料基板の表面に接着し、上記半導体
材料ウェハーを接着した上記基板の外周余白部に、硬質
セラ電ツク材からなる高さゲージを被着し、上記半導体
材料ウェハーの他面を高さゲージの上面を基準面として
メカノケミカル・lすVシンクにより超精密仕上げを施
こす複合基板の製造方法。 2 硬質セラ電ツク材からなる高さゲージの上面に、酸
化物、電化物、炭化物等の耐摩耗性薄膜を被着してなる
特許請求の範I21第1項記職の複合基板の製造方法。 3 メカノケ【カル・ポリッシングにより超精壷仕上げ
を行なった軟質磁性材料基板の表面に必要によ抄部縁薄
膜を被着し、その上に溶着用のハンダ材を被着し、次に
上記基板寸法よし小なる金属間化合物半導体材料ウェハ
ーの一面をメカノケミ力慶#キリVシングにより超精密
仕上げを行ない、その面上に絶縁薄膜を被着した後さら
に上記と同質の溶着用ハンダ材を被着し、上記基板と上
記半導体材料ウェハーとをそのハンダ材被着面で溶着接
合し、溶着接合後の上記基板の外周余白部に、硬質セラ
ミック材からなる高さゲージを被着し、上記半導体材料
ウェハーの他面を高さゲージの上置を基準面としてメカ
ノケミカル・ぼりッシング督ζより燗精書仕上げを施ζ
す複合基板の製造方法。 4 硬質セラミック材からなる高さゲージの上面に、酸
化物、窒化物、炭化物等の耐摩耗性薄膜を被着してな尋
特許請求の範srs項記職の複合基板。
[Claims] l An insulating thin film layer is deposited as necessary on the surface of a soft magnetic material substrate which has been subjected to ultra-precision finishing by mechanochemical bridging, and then a metal open compound semiconductor material wafer having dimensions smaller than the above substrate size is formed. A single stroke is given an ultra-precision finish by mechanochemical polishing, and the insulating thin film layer is adhered to the surface of the soft magnetic material substrate, and a hard ceramic is applied to the outer peripheral margin of the substrate to which the semiconductor material wafer is adhered. A method for manufacturing a composite substrate, in which a height gauge made of electrical material is adhered, and the other surface of the semiconductor material wafer is subjected to ultra-precision finishing using a mechanochemical V-sink using the upper surface of the height gauge as a reference surface. 2. Method for manufacturing a composite substrate as described in Claim I21, Paragraph 1, in which a wear-resistant thin film of oxide, electrification, carbide, etc. is applied to the upper surface of a height gauge made of hard ceramic electrical material. . 3 Mechanoke [Cover the surface of the soft magnetic material substrate, which has been given an ultra-fine finish by Cal polishing, with a thin film around the edges of the paper part if necessary, and then apply a solder material for welding on top of it, and then apply the above-mentioned substrate. Ultra-precision finishing is performed on one side of a small intermetallic compound semiconductor material wafer using Mechanochem Rikikei #Kiri V-singing, an insulating thin film is applied on that surface, and then a welding solder material of the same quality as above is applied. Then, the substrate and the semiconductor material wafer are welded together on their surfaces to which solder is applied, and a height gauge made of a hard ceramic material is adhered to the outer peripheral margin of the substrate after welding, and the semiconductor material is The other side of the wafer is given a fine finish using a mechanochemical polishing method using the top of the height gauge as a reference surface.
A method for manufacturing a composite substrate. 4. A composite substrate according to claim SRS, in which a wear-resistant thin film of oxide, nitride, carbide, etc. is coated on the upper surface of a height gauge made of a hard ceramic material.
JP56205644A 1981-12-18 1981-12-18 Manufacture of composite substrate Granted JPS58106883A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56205644A JPS58106883A (en) 1981-12-18 1981-12-18 Manufacture of composite substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56205644A JPS58106883A (en) 1981-12-18 1981-12-18 Manufacture of composite substrate

Publications (2)

Publication Number Publication Date
JPS58106883A true JPS58106883A (en) 1983-06-25
JPS638636B2 JPS638636B2 (en) 1988-02-23

Family

ID=16510299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56205644A Granted JPS58106883A (en) 1981-12-18 1981-12-18 Manufacture of composite substrate

Country Status (1)

Country Link
JP (1) JPS58106883A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01312828A (en) * 1988-04-13 1989-12-18 Philips Gloeilampenfab:Nv Manufacture of semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01312828A (en) * 1988-04-13 1989-12-18 Philips Gloeilampenfab:Nv Manufacture of semiconductor

Also Published As

Publication number Publication date
JPS638636B2 (en) 1988-02-23

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