JPS58101343A - Multiplication system - Google Patents

Abstract

PURPOSE:To reduce the bit width of a main adder and a peripheral circuit by using a cycle selecting the final sum component and the carry component from each multiplication part in the operation of vector operands. CONSTITUTION:An upper-order 4-byte of the final sum component of intermediate register 8-1 or 8-2 to which an output of a carry storage adder CSA is set, is set to a final sum register 14. An upper-order 4-byte of the final carry component of an intermediate register 9-1 or 9-2 is similarly set to a final carry register 15. A multiplexer 16 selects an accuracy guarantee carry of a flip-flop 11-1 or 11-2 to which an output of spill adders 10-1 and 10-2 is set and gives an output. The content of registers 14, 15 and an output of the multiplexer 16 are inputted to a main adder 12' of 32-bit width.

Description

[Detailed description of the invention]

(1) Technical field of the invention The present invention relates to a decoder for decoding a single multiplier, a multiple
It has a plurality of multiplication parts including a gate, a C8 m (carry save adder), a spill (split adder), and a main part into which the sum and carry output from the above multiplication part are inputted in a time-sharing manner. - In a multiplication device with an adder, the bit width of the main adder and peripheral circuit section can be reduced. (2) Prior art and problems Figure 1 shows a conventional multiplication device.

[, 1 is the input register where the multiplicand is set, 2 is the input register where the multiplier is set, 3 is the multiplexer, 4 is the decoder,
S is a multiple fist gate, 6 and 7 rings C8, 8 is an intermediate register where a thumb is set, 9 is an intermediate register where a carry is set, 1G is a spill adder, 11 is a 7 rip flip, 1 and 2 are Carrie Pupagesi Sergeant Y.
・Main adder made by adder, 13 indicates the result register, respectively. In the example shown in FIG. 1, the large registers 1.2 each have a 4-byte configuration. The multiplier t3 is first translated into the lowest order pi) (byte s) * tia, and finally pi) Ol-
select. The byte information selectively output from the multiplexer 3 is input to the decoder 4. The output of the decoder 4 is fed into a multiple gamer 5. The multiple gate 5 generates four types of multipliers Kl, Kl, Kl, based on the decode signals of the decoder 4, and the multipliers are multiplied by 1, , multiplied by 1, and multiplied by K1. Multiply it by 4 and manually input it to C856. The thumb and medium cum output from the CB Muro are input to the C8 module 7. At this time, the upper 4 bytes of intermediate register 8 and the upper 4 bytes of intermediate register 9 are also input to CBB10. The sum and carry output from the C8 module 1 are respectively input to intermediate registers 8.9. The least significant byte of intermediate register 8 and the least significant byte of intermediate register 9 are input to spill adder 10. In addition, the spill adder 10 has a flip-flop 11
The contents of are also input. The carry output from the spill adder 10 is set in the 7-lip active 11. At a predetermined tie, the contents of intermediate register 8, intermediate register 9, and arrival flop 11 are input to main φ adder 12, and the output of main adder 12 is set to result register 1B. In FIG. 1, input register 1 has a 32-bit configuration, and input register 1 to multiple gates)! ! The path from the multiplexer 3 to the reader 4 also has a 32-bit F configuration, and the path from the multiplexer 3 to the reader 4 has an 8-bit configuration. Intermediate registers 8 and 9 have a 5-byte configuration, and the path width from intermediate register 8 to main adder 12 and the path width from intermediate register to main adder are 40 bits. The path from intermediate register 8 to the input of C8 and 7 has a 3-path configuration, and from intermediate register 9 to CBB1
The path leading to 0 input also has a 32-pits configuration. The output of the main adder 12 is composed of 5 pi), but the least significant byte is discarded and only the upper 4 pi are sedated into the result register 13. In addition, input registers 1 and 2,
Decoder 4, Multiple Game) Black, C8 Muro and 7, Intermediate Regis I8 and 9, Spill Adder 10 and Tsurig e
? ■The knob 11 constitutes the S calculation part. No.! The figure is a time chart showing the operation of the first II multiplier. In FIG. 2, M is a wave number #1%B is a multiplier sC is a result operand, respectively. ml
When the calculation is commanded, the number is 11 (1)
The multiplication of is started. In addition, ml (1) is multiplier B pi) (Xu, 1 (odd is multiplier 1 pi)), 10) is multiplier B byte 1, and B (4) is multiplier B pi) O. There is. In the φ block, the multiplication of M x B (2) is started, and the sum component 8U (1) of M X B (1) output from Cs and the component C M (1) is intermediate register 8
．． 9 respectively. In the case of ÷3, the multiplication of M X B (3) is started. In addition, the top 4 bytes of M -XI (A and A and! Material 8U (1) and the Carry Ingredients C (1) are the top 4 bytes of the carrier 8U (2) and the carry ingredient C and are set in the intermediate registers 8.9, respectively.Furthermore, the lowest byte of the 4-sum component 8U(1) and the lowest byte of the carry component CM(1) are added to obtain the carry 1-R. (1) is set to 7 rip/fusep 11. In ÷4 evening stomach ivy, M xll (430 multiplication is started. Also, AXB (3), the upper 4 bytes of the sum component BUt, and the carry component C The sum of the upper 4 bytes of the sum component S and U (7) is separated into a sum component 8U (3) and a carry component C M (column) and set in intermediate registers /g and 9, respectively. Carry R (where I is 7 lip) generated when adding the least significant byte and carry component Cm(ri) and carry R(υ)
It is set to 1. +l$t4/, u in it, AXB(4) and tA formation 88U
(The sum of the upper 4 bytes of 31 and the upper 4 bytes of carry component C (3) is the sum of the upper 4 bytes of U (4) and the carry component C (4), each separated into intermediate register 8 and fIK
-kvF is applied. In addition, thumb component 8U (bottom pie F of I
and the carry component Cm (the least significant byte of the phrase and the carry 1 (
The carry R(a) that occurs when adding the
It is set to 11. Furthermore, the pie adder 12 is activated, and the addition of the sum component 5U (4) S, the middle component Cmu (4 and the carry R (to)) is performed. throne of output 4
The byte is set in result register 13. By the way, the multiplication S for the vector φ opend consists of a plurality of multiplication parts as shown in the 111th part and one main part.
Already configured with adder! In this type of multiplier proposed in I, it is necessary to transfer the sum component and carry component of 40 bits from each multiplication part to the main adder, and the paths and selection gates Ii'? The disadvantage is that the configuration is very complex. (31 Object of the Invention') The present invention eliminates the above-mentioned drawbacks, and provides a plurality of multiplication parts each consisting of a decoder for decoding a multiplier, a multiple gate, a Csmut tree, and a spill adder, and a In a multiplier that has one main adder into which output sum components, carry components, and numerical data for accuracy guarantee are input, the configuration of peripheral parts such as buses and selection gates from each multiplication part to the main adder is explained. It is our intention to provide a multiplication method & provide a multiplication method which can simplify the pitch width of the lK main bit adder by reducing the pit width by 5Kt. Multiplier register where multiplier is set,
a multiplicand register in which a number is set; a decoder that decodes the bit data extracted from the multiplicand register; a multiple contest gate that calculates a multiple of the multiplier based on the decoding result of the data;
A carry save adder tree into which the multiple of the multiplier from the gauge is input, an intermediate register for the (m+1) Xs width width, where the sum component output from the carry save adder tree is set, the above carry The carry component output from the save adder tree is set (horse ◆ 1) x % bit width bottom layer middle layer and the above ^ period middle layer bottom layer middle layer) and the above carry layer middle layer. 7. A plurality of multiplication parts consisting of a spill adder into which the least significant outer bit of the signal is input, the contents of the intermediate register for the above-mentioned sum, the contents of the intermediate register for the above-mentioned carrier, and the operation of the spill adder. In a multiplier having a carry propagation adder into which the result is input, the input operands to be multiplied are sent, one multiplication part is selected, and each of the multiplicand register I and multiplier register of the multiplication part is Set the multiplicand and the multiplier BY, and in the external multiplication part, take out the i'4NA bit data B() from the multiplier register, and use the decoder to write the bit data L(). , calculate the multiple of the wave multiplier using the above multiple φ game, and use the above carry-save adder tree to calculate M Tersu^ Ingredients 5U (a-
Calculate the sum of 1) and the carry component C(1-1) stored in the image during the carry period, and obtain the sub-component gtr(t) and the carry component C(i). After completing the process of setting the sum intermediate register and the carry intermediate register, respectively, and (b) the process of the above p),
Thumb component 8U of the above five-layer intermediate register I (bottom 1)
bit and the lowest 1 bit of the carry intermediate register are input to the spill adder, and the accuracy guarantee carry R(i-1) obtained in the previous cit! 'The above spill adder is manually loaded and the operation results are stored in ascending order for each of the first tome bit φ data to the first audience bit data of the multiplier register. After the above processes U) and 2) for the th audience bit data are completed, the carry propagation adder is used to add the contents of the sum intermediate register, the carry intermediate register, and the spill adder. The sum V of the calculation results is calculated as VlI mold. (5) Embodiments of the invention The present invention will be described below with reference to the drawings. FIG. 3 is a boot diagram of one embodiment of the present invention, and #I4 is a time chart showing its operation. In Figure 183, 1-1 and 1-8 are large registers, 2
-1 and 2-2 are also large registers, and 3-1 and 3-2 are! luteplex, 4 is data, s-1 and 5-2 are multiple gates, 6-1 and 6-2 are C&M, 7-1 and 7-2 are also C8, 8-1 and 8-2 are Sam. intermediate registers are set, 9-1 and 9-2 are intermediate registers where intermediate registers are set, 10-1 and 10-2 are spill adders, 11-
1 and 11-2 are 7 lip-flops, 12' is the main
13 is the result register, 14 is the final sum register, 1s is the final carry register, and 16 is the multiplexer, input registers 1-1 and 2- respectively.
1, multiplexer 3-1, decoder 4-1, multiple gate 5-1, C3A6-1 and 7-1, intermediate V
The I8-1 bit 9-1, the spill adder 1O-1 and the 7rip 7a tube 11-1 form the first multiplication part vIl, and similarly the large power registers 1-2 and 2-2, the multiplexer 3 -2, Desodor 4-2, Multiple gate 5-2, C3A6-2 and 7-2, Intermediate registers 8-2 and 9-2, Spill adder 10-2, Yohiflip 70
The knob 11-2 constitutes a second multiplication section. The first multiplication section and the second multiplication section have the same structure as the multiplication section of FIG. final sum register 1
4 is set to the upper 4 bytes of the final sum component of intermediate register 8-1 or 8-2. The final carry register 15 contains intermediate registers 9-1 or 9-! The upper 4 bytes of the final carry component of I are set. final sum e
Register 14 has a 4-byte configuration, and final carry register 15 also has a 4-byte configuration. multiplexer 16
selects and outputs the precision guarantee carry of 7 ripples 11-1 or 11-2. The main adder 12' contains the contents of the final sum register 14 and l&
Member Carey Regis 11 & contents and! Lutepre/! 16
The output and the input are input. The main adder 121 is 32 bits wide. The output of main adder 12' is set to result register IIK. FIG. 4 is a time chart showing the operation of the embodiment shown in FIG. As shown in No. 4111, first, the multiplicand AI
and multiplier B1 are input into the first multiplication section, and two cycles later, multiplicand A2 and multiplier B2 are input into the 20th multiplication section. First, the multiplication of AlXB1 will be explained. #l clock 2 starts multiplication of AlXB1[). At #2 clock, multiplication of AIXBl(2) is started, and AIXB1(2) output from C3A7-1 is started.
11 sum component S U 1 (1) and carry component C'
AI(1) is set in intermediate registers 8-1 and 9-1, respectively. At clock #3, multiplication of AIXBIQ31 is started. Also, A I X B 1 (21 and sum component 5U
(11 upper 4 bytes and carry component S A 1 (1
), the sum of the top four (ite) is the sum component S U 1 (2)
and the carry component CA1(2) is separated from the intermediate register 8.
-1.9-1 respectively. Furthermore, the sum component S U 1 (11 least significant bytes and the carry component C
A carry R1 (1) obtained by adding the least significant byte of A 1 (11) is set in the 7-lip flop 11-1. At the #4 clock, multiplication of AIXBl (4) is started. A t x B 1 (3) and the sum component S
The upper 4 bytes of U 1 (2) and the carry component Cmu 1 (
The sum of the phantom top four pies) is separated into sum component 8U1 (phrase and carry component CAl(3)K) and stored in intermediate register 8-1.9.
-1 respectively. Furthermore, Sam component 8U1
(21 least significant byte and carry component CA 1 (a)
Carry R1 (So is 7 rip-flops 11-1
is set to +5 cycles, M I
The sum of the upper 4 bytes of the data is separated into a sum component 8 U 1 (4) and a carry component CA 1 (4), which are each set in intermediate registers 18-1.9-1. Least significant byte and carry component CA 1
(The carry R1 (3) that occurs when adding the lowest byte of 39 and the carry R1 (3) is 7, and the
l-IK is set. In the $69 cycle, the upper 4 bytes of the sum component 8 U 1 (4) are set in the final sum register 14, and the upper 4 bytes of the carry component CA 1 (4) are set in the final life balance register 15#c. . In FIG. 4, X indicates the register 14, and Y indicates the register rsv. Also, the least significant byte of the sum component 8 U 1 (4) and the carry component Cmu 1 (the least significant of 4) (ite and carry R1 (8) & the carry R1 that occurs when added
(4 is put into the 7-lip a7ay-p1l-IK-, and the flip-flop 11-1 is set by the multiple converter 16.
The contents of are selectively output. In addition, Mayy Adder 12
' is activated, sum component 5Ul(+), carry component C
A 1 (4) and accuracy guarantee cache 9-Rl (4) are added. At +7! lock, the output of the main adder 12I is loaded into the result register IIK-%!. The multiplication of 2
Although the control means for performing such control is not shown in FIG. 3, the above control is possible! -c can be negative from the control 111iK of the iku4pqdaram or the bell logic. As is clear from a comparison between the multiplication device of FIG. 1 and the embodiment of FIG. c8
The pitch width has been reduced by a bit. By using Spill-77-10-1 and 10-2 for 4t cycles, the 1 point (ite σ) truncation performed in the 1st II σ) main adder 12 can be performed, and the bill adder 1
0-1.10-! This is because you are doing one force. If the 5:1 multiplication device has a plurality of multiplication parts as shown in FIG.
It is necessary to select the final sum and carry components of each multiplier and enter them into the main adder 12'; The present invention utilizes this selection cycle to select each spill adder 10.
-1.The result of 10-2 is reflected in the result operand, and the pitch width of the main adder and peripheral circuit part is reduced by 5K.
It is also possible to make the main adder v7/< it and supplement it with the 1 byte resulting from the remaining 1 byte spill adder. (6)! As is clear from the above description, the present invention has a plurality of multiplication parts each having a multiplier decoder, a C8 multiplier, and a spill adder. In the main game where the sum and carry outputted from the main adder and the carry are input in a time-divisional manner, it is possible to reduce the bits of the main adder and the peripheral a-contact portion.

[Brief explanation of drawings]

FIG. 1 is a boot diagram of a conventional multiplication device, FIG. 2 is a time chart showing its operation, FIG. 3 is a printer diagram of an embodiment of the present invention, and FIG. 4 is a time chart showing its operation. There are 1-1 and 1-2...input registers, 2-1 and 2-2.
・・Input register, 3-1 and 8-2・・・Multiple front panel, 4-・Decoder, 5-1 and 5-2・・・Multiple e-game), 6-1 and 6-2-・C8 system, γ -1 and 7-2・
...CS, 8-1 and 8-2... Intermediate registers where sum is set, 9-1 and 9-! ! ...Intermediate register where carry is set, 1G-1 and 10-2...δ Bill Adder, 11-1 and 11-2...Flip @ 7
El tube, 12'...Main adder, 13...
Result register, 14...Final sum e register j1.15
...Final carry register, 16...Multiplexer. Patent Applicant Fujitsu Kinsha Patent Attorney Kyotani 4'-X1 To Akane Waseda University Rashid 1+FI m12 1F3 11F4 $5 Book 61 4111 cases'l Bodhisattva 10CLKIIILII
III

Claims (1)

[Scope of Claims] A multiplier register in which the multiplier of book x dairy bits is 7 IF), a multiplicand register in which the multiplicand of trout x n bits is set in IF), a multiplicand register in which the multiplicand of trout x n bits is set as IF), and data of the interlocking bit taken out from the multiplicand register is decoded. a multiple gate that calculates a multiple of the multiplier based on the decoding result of the decoder;
A carry-save adder tree into which the multiple of the multiplier from the multiple Φ gate is input, and a sum component output from the carry-save adder tree is set (Kasumi ◆ 5) x Dairy convergence sum. The carry component output from the carry-save adder tree is set in the collapse intermediate register, the intermediate register I for the sum of the width (+1) x Tsuru Pi, and the lowest cross register of the sum layer intermediate register I. A plurality of multipliers are constructed of a spill adder into which the bit and the least significant bit of the carry intermediate register are input, as well as the contents of the sum intermediate register, the contents of the carry intermediate register, and the spill adder. A multiplication device with a carry propagation adder into which the result of the operation of adda, - is input. The multiplicand register and multiplier register l of the part are filled with a multiplier and a multiplier Bt, respectively.
- set, and in the mlI multiplication part, (to) the first 8th bit bit data B (receiver) from the multiplier register I, and the above data bit data/B (
The multiple gate is used to find the multiple of the multiplicand, and the carry-save adder series is used to store the multiplicand X1l(s) and the intermediate register for sum. 5U (t-1) and the above carry is stored in the middle layer and the carry component C (--
1), and calculate the sum component 11U(j) and the carry component C(j) obtained by VA respectively.
After completing the processing for N intermediate intermediate register carry, and (B) the processing in H) above, the sum component 8U of the intermediate register for ZUM (lowest path bit of R and L carry A process of manually inputting the least significant bit of the intermediate register for use in the spill adder, inputting the accuracy guarantee carry R (1-1) obtained in the previous Nicle to the spill adder, and storing the calculation result. are carried out in ascending order for each of the first bit bit data or the side bit bit Φdeme of the multiplier register, and the above processes (a) and (b) for the first bit bit Φdeme are performed on the first bit bit Φdeme of the multiplier register. After completion of the multiplication, the carry propagation adder is used to calculate the sum of the contents of the intermediate register for sum, the contents of the intermediate register for carry, and the operation result of the spill adder.