JPS58100300A - Cmos memory - Google Patents

Abstract

PURPOSE:To simplify the design by installing a power supply voltage detecting circuit and a logical operation circuit in an IC and to float each input pin by a power supply voltage drop signal. CONSTITUTION:A logical operation circuit section 3 and a power supply voltage detecting circuit section 4 are constituted by CMOSs and they are incorporated in an IC, and, at the same time, in addition to a chip select CS, other pins, for example, pins of address ADR, data input Din, write-enable WE, etc., are made reactive by using the output of the power supply voltage detecting circuit section 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMOS memory, and more particularly to a CMOS memory that has a built-in voltage detection circuit and can be backed up by a battery.

CMOS memory (Complemen) that includes static memory cells, address decoders, control circuits, etc.
taryMetal Oxide Sem1co
Since the inductor memory has extremely low power consumption, even in the event of a power outage, it can be used as a non-volatile memory like core memory with battery backup. When CMOS memory is used as a substantial nonvolatile memory, the CMOS memory is supplied with voltage from the battery when this system power supply is cut off, along with a system power supply for operating appropriate and peripheral circuits. Be it.

CMOS to enable battery backup
When a dedicated power down control terminal is provided for the memory, or when a chip select signal is supplied to the chip select terminal via the power down control circuit Z without providing a special control terminal. 7. However, in the former case, a dedicated control terminal must be provided in the IC (CMOS memory). In the latter case, as shown in Figure 1, the system power supply ■. When 0 is cut off, automatic vc
By configuring the cMO8 memory's power source to switch between the battery BAT and by providing the detection control unit 2 externally, it is possible to prevent memory contents from being destroyed by memory write signals that occur accidentally when the system power is turned on or off. In order to put the memory in a non-selected state so that the chip seleno (C8) signal is not selected, the chip seleno (C8) signal is forcibly set to the "0" level. That is, CMO'S memory 1
A detection control unit 2 is externally connected to the C8 terminal for Vc, and this detection control unit 2 includes a power supply voltage drop detection circuit PD and a logic between the output A of this detection circuit PD and the chip select signal B. A circuit iNR is provided. For the combination of the logical value of the output A of the detection port 13pD and the chip select signal B, the logical output from the detection control unit 2 is only when both the yc1 signals A and B are at the wO level as shown in FIG. It becomes "1". System power supply V
. 0 is cut off for some reason or becomes lower than the minimum voltage value, A=“1” and the output becomes “0” regardless of the value of the chip select signal +3 (C8). −
10,000, system power ■. When 0 is higher than the lowest voltage value and the value of the chip select signal (CS) is 0'', that is, when memory is selected, the output becomes 1'' and memory 1 is read.

Writing becomes possible.

FIG. 3 is an operational level diagram of the data relocation mode in the circuit of FIG.

For example, as shown in Figure 3 fa>, the system power supply ■c
c decreased from 5v to 2■, data retention
Once the mode is set, the power supply voltage drop detection output A'% is set to the "1" level as shown in Figure 3(b).
Set the select (CS) terminal t to ``0'' level. and,
As shown in FIG. 3(c), when the current consumption is 1°0, the operating current decreases from, for example, 040 mA to 1/jA. In other words, the power is maintained at a low power of 2 V x 1 μA = 2 μW.

According to the above configuration, the detection control section 2 needs to be externally attached to the CMOS memory in order to enable disassembly and backup, and the board design is complicated.

SUMMARY OF THE INVENTION In order to eliminate such drawbacks, it is an object of the present invention to provide a CMOS memory having a power down control function and a chip select function, which can be incorporated into a circuit'lcMO8 memory and which can have additional functions. .

Hereinafter, an embodiment of the present invention will be described with reference to FIG.

In the present invention, as shown in FIG.
It consists of a voltage detection circuit section 4y7cMO8, and is built into the IC, as well as a bin other than the chip select (C8), such as an address (ADH).

Data input (Din), write enable (WE)
) etc. also use the output of the voltage detection circuit section 4 to invalidate the input.

In the voltage detection circuit section 4 of FIG. 4, the power supply voltage V. 0 divided by high resistance R,, R, is applied to the gate of CMQ8.
Well, the power supply voltage ■. If 6 is royal level, P-M
The OSFET is turned on and 0 level appears at point A, and the power supply voltage ■. When C falls below the minimum voltage value, VC+
The i-cMos is turned off and the L'' level appears at point A. In the logic circuit section 3, the chip select signal (CS) and the output A of the voltage detection circuit section 4 are applied to the gate of CMO8. , configures a Noah gate, both inputs are 0”
Give the 17zal force ["1" for the level, and give the output "0" for other combinations.

In FIG. 4, the logic circuit section 3 controls only the chip select signal (C8) by the output of the voltage detection circuit section 4. However, the odor of the present invention is 0MO8
Other input bins of memory 1, e.g. address (A D
R), Data In (Din).

In order to make each bin of the write enable (WE) floating due to a drop in the power supply voltage, each input bin is provided with a logic circuit section, and signals such as address (ADR), data in (Din), etc. , FIG. 4 A NOR gate is taken with the output A of the pressure water f voltage detection circuit section 4, and the gate output signal Z is connected to each input bin.

As explained above, according to the present invention, the power supply voltage detection circuit and the logic circuit are incorporated into the IC, which simplifies the design, and also allows the input bins to be used not only for the chip select input bin but also for all other input bins. It can also be floated by a power supply voltage drop signal.

[Brief explanation of the drawing]

Figure 1 shows a cMos with battery backup function.
The configuration diagram of the memory, FIGS. 2 and 3 are respectively a logical operation explanation diagram and an operation level diagram in FIG. 1, and FIG. 4 is a configuration diagram of a CMOS memory showing an embodiment of the present invention.-1... CM □ S memory, 2... detection control section, 3
...Logic circuit section, 4...Voltage detection circuit section, C8...
・Chip select signal, ■oC...system power supply,
TRo” data retention mode period. 699- Complete (吃
Li.

Claims (1)

[Claims] A CMOS memory integrated into an IC, comprising a power supply voltage detection circuit and a circuit that takes logic between the output of the detection circuit and a control input signal.