JPS5791051A - Transmission code system - Google Patents

Transmission code system

Info

Publication number
JPS5791051A
JPS5791051A JP55166518A JP16651880A JPS5791051A JP S5791051 A JPS5791051 A JP S5791051A JP 55166518 A JP55166518 A JP 55166518A JP 16651880 A JP16651880 A JP 16651880A JP S5791051 A JPS5791051 A JP S5791051A
Authority
JP
Japan
Prior art keywords
character
bits
data
bit
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55166518A
Other languages
Japanese (ja)
Inventor
Tetsutada Shiga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP55166518A priority Critical patent/JPS5791051A/en
Publication of JPS5791051A publication Critical patent/JPS5791051A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To reduce the transmission cycle, by taking the head or final bit of a synchronizing character as 0, other bits as 1, and providing one or more 0-bits in the succeeding data character. CONSTITUTION:One frame A' in bit number (m) of one character consists of one synchronizing character B' and n pieces of data characters C'. The bit number of the synchronizing character B' is taken as 2m, the first or final bit is taken as 0, and other data are all set to 1. In the data character C' in m bits succeeding, one or more 0-bits are generated in the character without fail. Thus, the synchronization is checked at all times for detection, the redundancy bit is minimized, the transmission efficiency is increased and the transmission cycle can be decreased.
JP55166518A 1980-11-28 1980-11-28 Transmission code system Pending JPS5791051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55166518A JPS5791051A (en) 1980-11-28 1980-11-28 Transmission code system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55166518A JPS5791051A (en) 1980-11-28 1980-11-28 Transmission code system

Publications (1)

Publication Number Publication Date
JPS5791051A true JPS5791051A (en) 1982-06-07

Family

ID=15832800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55166518A Pending JPS5791051A (en) 1980-11-28 1980-11-28 Transmission code system

Country Status (1)

Country Link
JP (1) JPS5791051A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0216066A2 (en) * 1985-07-30 1987-04-01 Kabushiki Kaisha Toshiba Synchronisation system for digital information transmission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0216066A2 (en) * 1985-07-30 1987-04-01 Kabushiki Kaisha Toshiba Synchronisation system for digital information transmission

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