JPS5782269A - Tlb control system - Google Patents

Tlb control system

Info

Publication number
JPS5782269A
JPS5782269A JP55159154A JP15915480A JPS5782269A JP S5782269 A JPS5782269 A JP S5782269A JP 55159154 A JP55159154 A JP 55159154A JP 15915480 A JP15915480 A JP 15915480A JP S5782269 A JPS5782269 A JP S5782269A
Authority
JP
Japan
Prior art keywords
address
real
space
storage space
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55159154A
Other languages
Japanese (ja)
Inventor
Masahiro Kuriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55159154A priority Critical patent/JPS5782269A/en
Publication of JPS5782269A publication Critical patent/JPS5782269A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To keep constant the hit rate of address conversion of each virtual space, by providing a mapping corresponding table from logical address to real address for independent TLB(translation look aside buffer) at each virtual space. CONSTITUTION:The conversion from the logical address to the real address under the virtual storage space under present processing is made by obtaining the correspondence table 3-i of the TLB of the virtual space with a space instruction pointer 1 indicating the virtual storage space under processing from the TLB3 being correspondence tables 3-1-3-n from the logical address and real address sectioned at each virtual storage space. This is the same as the processing of a single virtual storage space, and the upper part of the logical address 2 and the logical page address of each entry of the correspondence table 3 are compared at a comparison circuit 4 and the real address is produced with the coupling between the real page address in the coincident entry and the lower part of the logical address 2.
JP55159154A 1980-11-11 1980-11-11 Tlb control system Pending JPS5782269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55159154A JPS5782269A (en) 1980-11-11 1980-11-11 Tlb control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55159154A JPS5782269A (en) 1980-11-11 1980-11-11 Tlb control system

Publications (1)

Publication Number Publication Date
JPS5782269A true JPS5782269A (en) 1982-05-22

Family

ID=15687441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55159154A Pending JPS5782269A (en) 1980-11-11 1980-11-11 Tlb control system

Country Status (1)

Country Link
JP (1) JPS5782269A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116050A (en) * 1983-11-28 1985-06-22 Nec Corp Address conversion system
JPS60118952A (en) * 1983-11-30 1985-06-26 Fujitsu Ltd Virtual address control system
JPH03218546A (en) * 1990-01-24 1991-09-26 Nec Corp Address conversion mechanism
JPH03244052A (en) * 1990-02-21 1991-10-30 Nec Corp Address conversion buffer device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116050A (en) * 1983-11-28 1985-06-22 Nec Corp Address conversion system
JPS60118952A (en) * 1983-11-30 1985-06-26 Fujitsu Ltd Virtual address control system
JPS6341102B2 (en) * 1983-11-30 1988-08-15 Fujitsu Ltd
JPH03218546A (en) * 1990-01-24 1991-09-26 Nec Corp Address conversion mechanism
JPH03244052A (en) * 1990-02-21 1991-10-30 Nec Corp Address conversion buffer device

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