JPS5780884A - Character pattern information input circuit - Google Patents
Character pattern information input circuitInfo
- Publication number
- JPS5780884A JPS5780884A JP15589680A JP15589680A JPS5780884A JP S5780884 A JPS5780884 A JP S5780884A JP 15589680 A JP15589680 A JP 15589680A JP 15589680 A JP15589680 A JP 15589680A JP S5780884 A JPS5780884 A JP S5780884A
- Authority
- JP
- Japan
- Prior art keywords
- pattern information
- character pattern
- signal
- circuit
- series
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Systems (AREA)
Abstract
PURPOSE:To prevent the malfunction for generation of a reset signal, by operating a control means in accordance with the reset signal, which is obtained from the bit synchronizing signal of character pattern information, to control the input of character pattern information to a series-parallel conversion means. CONSTITUTION:An FF circuit 22 generates a gate signal E, by which character pattern information is inputted to a series-parallel converting circuit 6 through a gate circuit 21, from the Q terminal by a reset signal C from a reset pulse generating circuit 2 connected to the S terminal and a set signal D, which is generated by detecting the horizontal synchronizing signal after the arrival of character pattern information, from a control signal generating circuit 9 connected to the R terminal. As the result, the gate circuit 21 is conductive to pass character pattern information from a waveform shaping circuit 1 through, and this information is inputted to the series-parallel converting circuit 6. Since character pattern information is applied to the series-parallel converting circuit 6 by the generation of the reset signal obtained by detecting a bit synchronizing signal RI, the input of the bit synchronizing signal before the generation of the reset signal is stopped.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15589680A JPS5780884A (en) | 1980-11-07 | 1980-11-07 | Character pattern information input circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15589680A JPS5780884A (en) | 1980-11-07 | 1980-11-07 | Character pattern information input circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5780884A true JPS5780884A (en) | 1982-05-20 |
JPS6155314B2 JPS6155314B2 (en) | 1986-11-27 |
Family
ID=15615869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15589680A Granted JPS5780884A (en) | 1980-11-07 | 1980-11-07 | Character pattern information input circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5780884A (en) |
-
1980
- 1980-11-07 JP JP15589680A patent/JPS5780884A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6155314B2 (en) | 1986-11-27 |
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