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Publication date
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Priority to JP1980147769UpriorityCriticalpatent/JPS6240449Y2/ja
Publication of JPS5771355UpublicationCriticalpatent/JPS5771355U/ja
Application grantedgrantedCritical
Publication of JPS6240449Y2publicationCriticalpatent/JPS6240449Y2/ja
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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Engineering & Computer Science
(AREA)
Computer Hardware Design
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Microelectronics & Electronic Packaging
(AREA)
Power Engineering
(AREA)
Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices
(AREA)