JPS5768956A - Failure retrieval system - Google Patents
Failure retrieval systemInfo
- Publication number
- JPS5768956A JPS5768956A JP14545480A JP14545480A JPS5768956A JP S5768956 A JPS5768956 A JP S5768956A JP 14545480 A JP14545480 A JP 14545480A JP 14545480 A JP14545480 A JP 14545480A JP S5768956 A JPS5768956 A JP S5768956A
- Authority
- JP
- Japan
- Prior art keywords
- speed conversion
- conversion circuit
- station
- signal
- transmission line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/40—Monitoring; Testing of relay systems
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
- Optical Communication System (AREA)
Abstract
PURPOSE:To enable failure retrieval in on-line, by alternately outputting coarse and fine pattern signals every half period of station assignment frequency, in a failure retrieval system of transmission line using binary code. CONSTITUTION:Speed conversion is made at a speed conversion circuit VC1 for inputted data, synchronizing bit is inserted and inputted to 3B, 4B conversion circuit BCT, and a dense pattern mode 1 and a coarse pattern mode 2 signals are outputted alternately every half period of signal frequency from a clock source f1 and transmitted to a transmission line L with precoding. In a relay device, the output of a playback device is brached and the signal component assigned to the station itself is picked up by inputting it to TFF and BPF and transferred to a terminal station. At a reception terminal station, decoding is made at a decoder DEC and converted into the signal in original bit number at an inversion circuit RECT, the speed conversion and synchronizing bit rejection are made at the speed conversion circuit VC2 to obtain the original data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14545480A JPS5768956A (en) | 1980-10-17 | 1980-10-17 | Failure retrieval system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14545480A JPS5768956A (en) | 1980-10-17 | 1980-10-17 | Failure retrieval system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5768956A true JPS5768956A (en) | 1982-04-27 |
Family
ID=15385596
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14545480A Pending JPS5768956A (en) | 1980-10-17 | 1980-10-17 | Failure retrieval system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5768956A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58215829A (en) * | 1982-06-09 | 1983-12-15 | Nec Corp | Locating system of fault in repeater |
-
1980
- 1980-10-17 JP JP14545480A patent/JPS5768956A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58215829A (en) * | 1982-06-09 | 1983-12-15 | Nec Corp | Locating system of fault in repeater |
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