JPS5745760A - Packet transmission system - Google Patents
Packet transmission systemInfo
- Publication number
- JPS5745760A JPS5745760A JP55120183A JP12018380A JPS5745760A JP S5745760 A JPS5745760 A JP S5745760A JP 55120183 A JP55120183 A JP 55120183A JP 12018380 A JP12018380 A JP 12018380A JP S5745760 A JPS5745760 A JP S5745760A
- Authority
- JP
- Japan
- Prior art keywords
- packet
- transmission
- processing speed
- data processing
- reception side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
PURPOSE:To increase the data transmission efficiency of a packet network, by reducing the control information such as packet request, through the transmission of each packet with a prescribed interval in matching with a data processing speed at reception side. CONSTITUTION:At line connection calling out a reception side DPR in response to a call of a transmission side DPS, a transmission side exchanger of an exchange network PN corresponds the identification signal with a memory center storing the identification and functional information of the reception side DPR by means of protocol. As a result, a transmission side exchanger knows the data processing speed and the reception buffer memory capacity of the reception side and gives it to the transmission side DPS. The transmission side DPS reads in the packet data length corresponding to the data processing speed and sets it to a packet processor PA. Thus, each packet is transmitted with a prescribed interval in matching with the data processing speed of the reception side DPR.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55120183A JPS5745760A (en) | 1980-08-30 | 1980-08-30 | Packet transmission system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55120183A JPS5745760A (en) | 1980-08-30 | 1980-08-30 | Packet transmission system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5745760A true JPS5745760A (en) | 1982-03-15 |
Family
ID=14779960
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55120183A Pending JPS5745760A (en) | 1980-08-30 | 1980-08-30 | Packet transmission system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5745760A (en) |
-
1980
- 1980-08-30 JP JP55120183A patent/JPS5745760A/en active Pending
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