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Priority to JP1976162066UpriorityCriticalpatent/JPS5727173Y2/ja
Publication of JPS5378962UpublicationCriticalpatent/JPS5378962U/ja
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Publication of JPS5727173Y2publicationCriticalpatent/JPS5727173Y2/ja
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/93—Batch processes
H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting