JPS5721398Y2 - - Google Patents
Info
- Publication number
- JPS5721398Y2 JPS5721398Y2 JP1974150556U JP15055674U JPS5721398Y2 JP S5721398 Y2 JPS5721398 Y2 JP S5721398Y2 JP 1974150556 U JP1974150556 U JP 1974150556U JP 15055674 U JP15055674 U JP 15055674U JP S5721398 Y2 JPS5721398 Y2 JP S5721398Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1974150556U JPS5721398Y2 (en:Method) | 1974-12-11 | 1974-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1974150556U JPS5721398Y2 (en:Method) | 1974-12-11 | 1974-12-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5177014U JPS5177014U (en:Method) | 1976-06-17 |
| JPS5721398Y2 true JPS5721398Y2 (en:Method) | 1982-05-10 |
Family
ID=28442248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1974150556U Expired JPS5721398Y2 (en:Method) | 1974-12-11 | 1974-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5721398Y2 (en:Method) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3343092A (en) * | 1963-10-29 | 1967-09-19 | Gen Electric | Afc disabling system operative by reducing the d.c. discriminator output to zero |
| JPS5120711U (en:Method) * | 1974-07-31 | 1976-02-16 |
-
1974
- 1974-12-11 JP JP1974150556U patent/JPS5721398Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5177014U (en:Method) | 1976-06-17 |