JPS57196139A - Processing circuit for defect detecting signal - Google Patents
Processing circuit for defect detecting signalInfo
- Publication number
- JPS57196139A JPS57196139A JP8012881A JP8012881A JPS57196139A JP S57196139 A JPS57196139 A JP S57196139A JP 8012881 A JP8012881 A JP 8012881A JP 8012881 A JP8012881 A JP 8012881A JP S57196139 A JPS57196139 A JP S57196139A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- scanning period
- edge
- delayed
- theoretical product
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
Abstract
PURPOSE:To detect a size of a defect from a theoretical product output of a first signal, which indicates a period extending from a scanning start of a binary-coded image signal to detection of fall edge and a second signal ranging from an edge of a signal, which is delayed by a full scanning period and is inversed, to completion of a scanning. CONSTITUTION:A shift register 1 is a circuit which delays a binary-coded signal input A by a full scanning period to output it. If an initial rise detecting circuit 3 detects an initial rise edge of a wave-form of the signal intput A, delayed by a full scanning period, it outputs a high-level signal till terminal of a scanning period. A final fall detecting circuit 2 detects a final fall edge (d) of the signal input A to set an amount, being equivalent to a time extending from a start point of a scanning period to the edge (d), in a down counter 4 which outputs a high level till a count zero. Thus, a theoretical product of an inversion output of a signal wave form A, delayed by a full scanning period, and a theoretical product of signal wave-forms B and C are formed in a theoretical product circuit 5, and this permits obtaining of a signal, indicating a size of a defect, in a D.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8012881A JPS57196139A (en) | 1981-05-28 | 1981-05-28 | Processing circuit for defect detecting signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8012881A JPS57196139A (en) | 1981-05-28 | 1981-05-28 | Processing circuit for defect detecting signal |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57196139A true JPS57196139A (en) | 1982-12-02 |
JPS6355654B2 JPS6355654B2 (en) | 1988-11-04 |
Family
ID=13709575
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8012881A Granted JPS57196139A (en) | 1981-05-28 | 1981-05-28 | Processing circuit for defect detecting signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57196139A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5257876A (en) * | 1975-11-07 | 1977-05-12 | Fuji Electric Co Ltd | Fruit flaw identifying apparatus |
JPS55161486A (en) * | 1979-05-31 | 1980-12-16 | Fuji Electric Co Ltd | Defect detection system |
-
1981
- 1981-05-28 JP JP8012881A patent/JPS57196139A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5257876A (en) * | 1975-11-07 | 1977-05-12 | Fuji Electric Co Ltd | Fruit flaw identifying apparatus |
JPS55161486A (en) * | 1979-05-31 | 1980-12-16 | Fuji Electric Co Ltd | Defect detection system |
Also Published As
Publication number | Publication date |
---|---|
JPS6355654B2 (en) | 1988-11-04 |
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