JPS57192149A - Data transmission controlling system - Google Patents
Data transmission controlling systemInfo
- Publication number
- JPS57192149A JPS57192149A JP56076680A JP7668081A JPS57192149A JP S57192149 A JPS57192149 A JP S57192149A JP 56076680 A JP56076680 A JP 56076680A JP 7668081 A JP7668081 A JP 7668081A JP S57192149 A JPS57192149 A JP S57192149A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- data
- line
- transmitter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Selective Calling Equipment (AREA)
Abstract
PURPOSE:To transmit a function data surely, by transmitting the information corresponding to a prescribed time, through the stop of a clock signal continuously transmitted for the prescribed time, in transmitting data together with the clock signal between transmission and reception terminal stations. CONSTITUTION:A data transmitter 1 and a data receiver 2 are connected with a data line 3 and a clock line 4, and a clock from the receiver 2 is received at a controller of the transmitter 1 via the line 4. The clock is applied to an OR gate 10 and supplied to a shift register 8 with a signal on a clock line 9 in the transmitter. In this case, the clock incoming is counted with the controller 6 and the signal is periodically outputted on the line according to the result of count, and the data inputted from a data line 7 in the transmitter to the register 8 is renewed with the output of the gate 10. The transmission of the clock is stopped at each prescribed time and the function data can surely be transmitted with a simple constitution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56076680A JPS57192149A (en) | 1981-05-22 | 1981-05-22 | Data transmission controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56076680A JPS57192149A (en) | 1981-05-22 | 1981-05-22 | Data transmission controlling system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57192149A true JPS57192149A (en) | 1982-11-26 |
Family
ID=13612139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56076680A Pending JPS57192149A (en) | 1981-05-22 | 1981-05-22 | Data transmission controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57192149A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59186451A (en) * | 1983-04-08 | 1984-10-23 | Fujitsu Ltd | Data transmission system |
-
1981
- 1981-05-22 JP JP56076680A patent/JPS57192149A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59186451A (en) * | 1983-04-08 | 1984-10-23 | Fujitsu Ltd | Data transmission system |
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