JPS57185536A - General-purpose i/o controller - Google Patents

General-purpose i/o controller

Info

Publication number
JPS57185536A
JPS57185536A JP56070951A JP7095181A JPS57185536A JP S57185536 A JPS57185536 A JP S57185536A JP 56070951 A JP56070951 A JP 56070951A JP 7095181 A JP7095181 A JP 7095181A JP S57185536 A JPS57185536 A JP S57185536A
Authority
JP
Japan
Prior art keywords
cpu
data
format
rom49
read out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56070951A
Other languages
Japanese (ja)
Inventor
Hidetaka Fujisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP56070951A priority Critical patent/JPS57185536A/en
Publication of JPS57185536A publication Critical patent/JPS57185536A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

PURPOSE:To make a CPU and an I/O suitable for each other, even if the data format of the CPU is changed or extended, by discriminating the data format from the CPU and performing a data processing in matching with the format. CONSTITUTION:A specific data format given for a CPU is discriminated with an operation circuit 45 through machine type data 11 and format data FD12 from the CPU, and a data corresponding to the fromat discriminated at the circuit 45 is read out of various control data stored in an ROM49 in advance. The control data read out of the ROM49 is decoded at an operation decoder 41 to read out the data from the CPU and a printer 51 is controlled via a print controller 50. Thus, even if the data format of the CPU is extended or changed, the CPU and the printer can be matched by only changing a part of the ROM49.
JP56070951A 1981-05-12 1981-05-12 General-purpose i/o controller Pending JPS57185536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56070951A JPS57185536A (en) 1981-05-12 1981-05-12 General-purpose i/o controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56070951A JPS57185536A (en) 1981-05-12 1981-05-12 General-purpose i/o controller

Publications (1)

Publication Number Publication Date
JPS57185536A true JPS57185536A (en) 1982-11-15

Family

ID=13446316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56070951A Pending JPS57185536A (en) 1981-05-12 1981-05-12 General-purpose i/o controller

Country Status (1)

Country Link
JP (1) JPS57185536A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029863A (en) * 1983-07-12 1985-02-15 Fuji Electric Co Ltd Decentralized type information processing system
JPS63241651A (en) * 1987-03-30 1988-10-06 Toshiba Eng Co Ltd Data transfer device
WO1989001666A1 (en) * 1987-08-12 1989-02-23 Fanuc Ltd I/o module control system
US4863538A (en) * 1986-10-17 1989-09-05 Board Of Regents, The University Of Texas System Method and apparatus for producing parts by selective sintering
US4944817A (en) * 1986-10-17 1990-07-31 Board Of Regents, The University Of Texas System Multiple material systems for selective beam sintering
US5017317A (en) * 1989-12-04 1991-05-21 Board Of Regents, The Uni. Of Texas System Gas phase selective beam deposition
US5017753A (en) * 1986-10-17 1991-05-21 Board Of Regents, The University Of Texas System Method and apparatus for producing parts by selective sintering
EP0507540A2 (en) * 1991-04-01 1992-10-07 Ge Fanuc Automation North America, Inc. Method for operating a networked computer system to minimize data conversion overhead

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029863A (en) * 1983-07-12 1985-02-15 Fuji Electric Co Ltd Decentralized type information processing system
US4863538A (en) * 1986-10-17 1989-09-05 Board Of Regents, The University Of Texas System Method and apparatus for producing parts by selective sintering
US4938816A (en) * 1986-10-17 1990-07-03 Board Of Regents, The University Of Texas System Selective laser sintering with assisted powder handling
US4944817A (en) * 1986-10-17 1990-07-31 Board Of Regents, The University Of Texas System Multiple material systems for selective beam sintering
US5017753A (en) * 1986-10-17 1991-05-21 Board Of Regents, The University Of Texas System Method and apparatus for producing parts by selective sintering
JPS63241651A (en) * 1987-03-30 1988-10-06 Toshiba Eng Co Ltd Data transfer device
WO1989001666A1 (en) * 1987-08-12 1989-02-23 Fanuc Ltd I/o module control system
US5017317A (en) * 1989-12-04 1991-05-21 Board Of Regents, The Uni. Of Texas System Gas phase selective beam deposition
EP0507540A2 (en) * 1991-04-01 1992-10-07 Ge Fanuc Automation North America, Inc. Method for operating a networked computer system to minimize data conversion overhead

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