JPS57155646A - Error correcting and error correcting code generating circuit in combination - Google Patents

Error correcting and error correcting code generating circuit in combination

Info

Publication number
JPS57155646A
JPS57155646A JP56041505A JP4150581A JPS57155646A JP S57155646 A JPS57155646 A JP S57155646A JP 56041505 A JP56041505 A JP 56041505A JP 4150581 A JP4150581 A JP 4150581A JP S57155646 A JPS57155646 A JP S57155646A
Authority
JP
Japan
Prior art keywords
error correcting
information
bytes
plus
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56041505A
Other languages
Japanese (ja)
Other versions
JPS6132700B2 (en
Inventor
Katsumi Fujinami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56041505A priority Critical patent/JPS57155646A/en
Publication of JPS57155646A publication Critical patent/JPS57155646A/en
Publication of JPS6132700B2 publication Critical patent/JPS6132700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To obtain the titled circuit which is suited to a high degree of integration, by using the same terminal to the input of an error correcting code or the input of the result of an exclusive OR which is applied from outside in accordance with the information byte width of the error correcting subject. CONSTITUTION:The internal logical block is equal between logical blocks 13 and 13'. These blocks 13 and 13' comprise code producers/decoders 1 and 1' of the 1st arithmetic means, output means 6 and 6', shared input terminal groups 73-76, byte width designators 2 and 2' of a selecting means, comparators 3 and 3' of the 2nd arithmetic means, discriminators 4 and 4' of a decoding means, and correctors 5 and 5'. The information B01 of 2 bytes of the first half and the information B23 of 2 bytes of the second half among the information of 4 bytes are applied to terminals 10 and 10' respectively. The decoder 1 receives an error correcting code of 4 bits corresponding to the information code of 2 bytes applied to terminals 10 plus 71-74 and produces arithmetic results CS0-CS5. These arithmetic results are supplied to the comparator 3 as well as to terminals 75', 76' plus 81'-84' of the block 13' through the terminal 6. Thus syndromes S0, S6 plus S'0-S'6 corresponding to error correcting codes C0-C6 are delivered.
JP56041505A 1981-03-20 1981-03-20 Error correcting and error correcting code generating circuit in combination Granted JPS57155646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56041505A JPS57155646A (en) 1981-03-20 1981-03-20 Error correcting and error correcting code generating circuit in combination

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56041505A JPS57155646A (en) 1981-03-20 1981-03-20 Error correcting and error correcting code generating circuit in combination

Publications (2)

Publication Number Publication Date
JPS57155646A true JPS57155646A (en) 1982-09-25
JPS6132700B2 JPS6132700B2 (en) 1986-07-29

Family

ID=12610217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56041505A Granted JPS57155646A (en) 1981-03-20 1981-03-20 Error correcting and error correcting code generating circuit in combination

Country Status (1)

Country Link
JP (1) JPS57155646A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009510875A (en) * 2005-09-28 2009-03-12 エイティーアイ・テクノロジーズ，インコーポレイテッド Method and apparatus for error management

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009510875A (en) * 2005-09-28 2009-03-12 エイティーアイ・テクノロジーズ，インコーポレイテッド Method and apparatus for error management
US8667375B2 (en) 2005-09-28 2014-03-04 Ati Technologies Ulc Method and apparatus for error management
US8769384B2 (en) 2005-09-28 2014-07-01 Ati Technologies Ulc Method and apparatus for error management

Also Published As

Publication number Publication date
JPS6132700B2 (en) 1986-07-29

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