JPS5715524A - Receiver - Google Patents
ReceiverInfo
- Publication number
- JPS5715524A JPS5715524A JP9149680A JP9149680A JPS5715524A JP S5715524 A JPS5715524 A JP S5715524A JP 9149680 A JP9149680 A JP 9149680A JP 9149680 A JP9149680 A JP 9149680A JP S5715524 A JPS5715524 A JP S5715524A
- Authority
- JP
- Japan
- Prior art keywords
- display device
- channel
- decoder
- displayed
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
- H03J1/02—Indicating arrangements
- H03J1/04—Indicating arrangements with optical indicating means
- H03J1/045—Indication of the tuning band, the bandwidth, tone control, the channel number, the frequency, or the like
- H03J1/047—Indication of the tuning band, the bandwidth, tone control, the channel number, the frequency, or the like using electronic means, e.g. LED's
- H03J1/048—Indication of the tuning band, the bandwidth, tone control, the channel number, the frequency, or the like using electronic means, e.g. LED's with digital indication
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
PURPOSE:To simplify the circuit constitution and to reduce the cost, by digitally displaying the channel number of a plurality of preset channels with one display device. CONSTITUTION:A decoder 22 converts on/off of channel switches 6-10 to a segment driving signal of a display device 21. The frequency stored in the channel memory is digitally displayed on the display device 21 with outputs Seg1-Seg3 of a decoder 20 by depressing arbitrary channel switches 6-10. The channel number is displayed on the display device 21 with the output Seg4 from the decoder 22 corresponding to the channel switch depressed at the same time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9149680A JPS5715524A (en) | 1980-07-03 | 1980-07-03 | Receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9149680A JPS5715524A (en) | 1980-07-03 | 1980-07-03 | Receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5715524A true JPS5715524A (en) | 1982-01-26 |
Family
ID=14028016
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9149680A Pending JPS5715524A (en) | 1980-07-03 | 1980-07-03 | Receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5715524A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5598057U (en) * | 1978-12-27 | 1980-07-08 |
-
1980
- 1980-07-03 JP JP9149680A patent/JPS5715524A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5598057U (en) * | 1978-12-27 | 1980-07-08 |
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