JPS57124170U - - Google Patents
Info
- Publication number
- JPS57124170U JPS57124170U JP1981010726U JP1072681U JPS57124170U JP S57124170 U JPS57124170 U JP S57124170U JP 1981010726 U JP1981010726 U JP 1981010726U JP 1072681 U JP1072681 U JP 1072681U JP S57124170 U JPS57124170 U JP S57124170U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981010726U JPS57124170U (en) | 1981-01-28 | 1981-01-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981010726U JPS57124170U (en) | 1981-01-28 | 1981-01-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57124170U true JPS57124170U (en) | 1982-08-03 |
Family
ID=29808874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981010726U Pending JPS57124170U (en) | 1981-01-28 | 1981-01-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57124170U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018511175A (en) * | 2015-03-16 | 2018-04-19 | パック テック−パッケージング テクノロジーズ ゲーエムベーハー | Chip arrangement and method for forming contact connections |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53760B2 (en) * | 1973-05-07 | 1978-01-11 |
-
1981
- 1981-01-28 JP JP1981010726U patent/JPS57124170U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53760B2 (en) * | 1973-05-07 | 1978-01-11 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018511175A (en) * | 2015-03-16 | 2018-04-19 | パック テック−パッケージング テクノロジーズ ゲーエムベーハー | Chip arrangement and method for forming contact connections |