JPS57116480A - Facsimile equipment - Google Patents
Facsimile equipmentInfo
- Publication number
- JPS57116480A JPS57116480A JP56002156A JP215681A JPS57116480A JP S57116480 A JPS57116480 A JP S57116480A JP 56002156 A JP56002156 A JP 56002156A JP 215681 A JP215681 A JP 215681A JP S57116480 A JPS57116480 A JP S57116480A
- Authority
- JP
- Japan
- Prior art keywords
- block
- counter
- signal
- comparator
- transmission time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/41—Bandwidth or redundancy reduction
- H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
Abstract
PURPOSE:To vary minimum transmission time optionally while securing the minimum transmission time with simple constitution by counting the number of every block of transmitted data, by comparing it with given data, and by adding an insignificant bit. CONSTITUTION:Image information from a scanner 1 is coded, block by block, by a coder 4 and a synchronizing code is added to generate an output; when the synchronizing code of each block is generated, a bit-number counter 7 is reset, and every time the coding processing of the image information ends, access to a comparator 8 is attained. When a signal from the comparator 8 is not supplied to a switch circuit 6, the output of the coder 4 is applied as transmitted data to the counter 7 and when the signal is supplied, a signal from an insignificant- bit generator 5 is applied to the counter 7. Then, data from a latch circuit 9 is compared by the comparator 8 with the count value of the counter 7 for every block to vary minimum transmission time optionally, thereby sending an image signal from a modem 3 to a circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56002156A JPS57116480A (en) | 1981-01-12 | 1981-01-12 | Facsimile equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56002156A JPS57116480A (en) | 1981-01-12 | 1981-01-12 | Facsimile equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57116480A true JPS57116480A (en) | 1982-07-20 |
Family
ID=11521482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56002156A Pending JPS57116480A (en) | 1981-01-12 | 1981-01-12 | Facsimile equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57116480A (en) |
-
1981
- 1981-01-12 JP JP56002156A patent/JPS57116480A/en active Pending
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