JPS5711554A - Frame synchronizing system - Google Patents
Frame synchronizing systemInfo
- Publication number
- JPS5711554A JPS5711554A JP8533580A JP8533580A JPS5711554A JP S5711554 A JPS5711554 A JP S5711554A JP 8533580 A JP8533580 A JP 8533580A JP 8533580 A JP8533580 A JP 8533580A JP S5711554 A JPS5711554 A JP S5711554A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock
- frame
- synchronism
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
Abstract
PURPOSE:To prevent out of frame synchronism, by detecting the momentary interruption through the provision of a memory circuit having a phase locked loop between a code conversion circuit and a frame synchronizing circuit and providing a means to stop out of the frame synchronism. CONSTITUTION:A consecutive clock of a signal from a trnamission line 3 is picked up by a code conversion circuit 1 for data reproduction. The reproduced data is written in a memory circuit 5 and read out with the clock from a phase locked loop 6 in synchronism depending on the clock from the circuit 1 to transmit the clock and the data to a frame synchronizing circuit. Even if momentary interruption is caused and the clock from the circuit 1 is interrupted, since the clock is supplied from the circuit 6, the count of a circuit 2 is not stopped. As the data in this case, since inaccurate information is transmitted to the frame synchronism, the out of frame synchronism can be avoided by the output of a momentary interruption detecting circuit 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8533580A JPS5711554A (en) | 1980-06-24 | 1980-06-24 | Frame synchronizing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8533580A JPS5711554A (en) | 1980-06-24 | 1980-06-24 | Frame synchronizing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5711554A true JPS5711554A (en) | 1982-01-21 |
Family
ID=13855762
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8533580A Pending JPS5711554A (en) | 1980-06-24 | 1980-06-24 | Frame synchronizing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5711554A (en) |
-
1980
- 1980-06-24 JP JP8533580A patent/JPS5711554A/en active Pending
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