JPS5711554A - Frame synchronizing system - Google Patents

Frame synchronizing system

Info

Publication number
JPS5711554A
JPS5711554A JP8533580A JP8533580A JPS5711554A JP S5711554 A JPS5711554 A JP S5711554A JP 8533580 A JP8533580 A JP 8533580A JP 8533580 A JP8533580 A JP 8533580A JP S5711554 A JPS5711554 A JP S5711554A
Authority
JP
Japan
Prior art keywords
circuit
clock
frame
synchronism
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8533580A
Other languages
Japanese (ja)
Inventor
Toshio Ikeda
Yuzo Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8533580A priority Critical patent/JPS5711554A/en
Publication of JPS5711554A publication Critical patent/JPS5711554A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0083Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

PURPOSE:To prevent out of frame synchronism, by detecting the momentary interruption through the provision of a memory circuit having a phase locked loop between a code conversion circuit and a frame synchronizing circuit and providing a means to stop out of the frame synchronism. CONSTITUTION:A consecutive clock of a signal from a trnamission line 3 is picked up by a code conversion circuit 1 for data reproduction. The reproduced data is written in a memory circuit 5 and read out with the clock from a phase locked loop 6 in synchronism depending on the clock from the circuit 1 to transmit the clock and the data to a frame synchronizing circuit. Even if momentary interruption is caused and the clock from the circuit 1 is interrupted, since the clock is supplied from the circuit 6, the count of a circuit 2 is not stopped. As the data in this case, since inaccurate information is transmitted to the frame synchronism, the out of frame synchronism can be avoided by the output of a momentary interruption detecting circuit 4.
JP8533580A 1980-06-24 1980-06-24 Frame synchronizing system Pending JPS5711554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8533580A JPS5711554A (en) 1980-06-24 1980-06-24 Frame synchronizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8533580A JPS5711554A (en) 1980-06-24 1980-06-24 Frame synchronizing system

Publications (1)

Publication Number Publication Date
JPS5711554A true JPS5711554A (en) 1982-01-21

Family

ID=13855762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8533580A Pending JPS5711554A (en) 1980-06-24 1980-06-24 Frame synchronizing system

Country Status (1)

Country Link
JP (1) JPS5711554A (en)

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