JPS57112029A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57112029A
JPS57112029A JP18708480A JP18708480A JPS57112029A JP S57112029 A JPS57112029 A JP S57112029A JP 18708480 A JP18708480 A JP 18708480A JP 18708480 A JP18708480 A JP 18708480A JP S57112029 A JPS57112029 A JP S57112029A
Authority
JP
Japan
Prior art keywords
substrate
mount
pad
polished
abutting against
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18708480A
Other languages
Japanese (ja)
Other versions
JPS6140130B2 (en
Inventor
Akira Tabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18708480A priority Critical patent/JPS57112029A/en
Publication of JPS57112029A publication Critical patent/JPS57112029A/en
Publication of JPS6140130B2 publication Critical patent/JPS6140130B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To realize an even polishing by a method wherein a substrate to be polished is wax fixed on the lower surface of the first mount and a cushion is sandwiched between the second mount that is rotary and its pad abutting against the substrate. CONSTITUTION:Wax is used to attach to the lower surface of the first mount 21 a substrate 23 a side whereof is to be polished. Abutting against the substrate 23 is a pad 25 examplifiedly made of buckskin mounted on the second mount 22 that rotates so that the pad 25 may polish the substrate 23. Interposing between the second mount 22 and the pad 25 is a cushioning material 26 which can be a packing material consisting of two films of synthesized plastic sandwiching a multiplicity of tiny air bubbles or sponge. Mechanical stress generated by the curvature or uneveness of the substrate surface if absorbed by the cushioning material 26, which results in an even, overall polish.
JP18708480A 1980-12-29 1980-12-29 Manufacture of semiconductor device Granted JPS57112029A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18708480A JPS57112029A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18708480A JPS57112029A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57112029A true JPS57112029A (en) 1982-07-12
JPS6140130B2 JPS6140130B2 (en) 1986-09-08

Family

ID=16199838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18708480A Granted JPS57112029A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57112029A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103567857A (en) * 2013-11-04 2014-02-12 上海申和热磁电子有限公司 Double-sided polishing process for silicon wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103567857A (en) * 2013-11-04 2014-02-12 上海申和热磁电子有限公司 Double-sided polishing process for silicon wafer

Also Published As

Publication number Publication date
JPS6140130B2 (en) 1986-09-08

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