JPS57105054A - Monitor device for program debug - Google Patents

Monitor device for program debug

Info

Publication number
JPS57105054A
JPS57105054A JP55182308A JP18230880A JPS57105054A JP S57105054 A JPS57105054 A JP S57105054A JP 55182308 A JP55182308 A JP 55182308A JP 18230880 A JP18230880 A JP 18230880A JP S57105054 A JPS57105054 A JP S57105054A
Authority
JP
Japan
Prior art keywords
input
output
instruction
computer
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55182308A
Other languages
Japanese (ja)
Inventor
Shinichi Terajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55182308A priority Critical patent/JPS57105054A/en
Publication of JPS57105054A publication Critical patent/JPS57105054A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Abstract

PURPOSE:To facilitate the easy confirmation for a processed program without having any combination with an input/output device, by providing a function which sets optionally a device address to discriminate the desired input/output device puls a function which responds to a specific input/output instruction to a computer. CONSTITUTION:A monitor device 3 for program debug is connected to a digital electronic computer via bus line 2 through which an input data and various types of control signals are transmitted. Thus the monitoring is possible for the program debug and overall working of the computer control system. A device address is optionally set at an address setting part 3a of the device so that the computer can discriminate an input/output device. As a result, the computer can respond to an input/output instruction. Then an instruction is decoded by an input/output instruction decoder 3b of the device 3, and a specific input/output instruction is selected at an input/output instruction selecting part 3c. This selected instruction is supplied to input and output data storage parts 3e and 3f, a data input part 3j, an output data display part 3g and an output data converting part 3h respectively. In such a way, a processed program can be easily confirmed.
JP55182308A 1980-12-23 1980-12-23 Monitor device for program debug Pending JPS57105054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182308A JPS57105054A (en) 1980-12-23 1980-12-23 Monitor device for program debug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182308A JPS57105054A (en) 1980-12-23 1980-12-23 Monitor device for program debug

Publications (1)

Publication Number Publication Date
JPS57105054A true JPS57105054A (en) 1982-06-30

Family

ID=16116015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182308A Pending JPS57105054A (en) 1980-12-23 1980-12-23 Monitor device for program debug

Country Status (1)

Country Link
JP (1) JPS57105054A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034645U (en) * 1983-08-10 1985-03-09 三菱電機株式会社 Simulated transfer response signal generator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826412A (en) * 1971-08-10 1973-04-07
JPS5247342A (en) * 1975-10-14 1977-04-15 Mitsubishi Electric Corp Real time simulation system of input/output unit
JPS55159257A (en) * 1979-05-30 1980-12-11 Mitsubishi Electric Corp Debugging system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826412A (en) * 1971-08-10 1973-04-07
JPS5247342A (en) * 1975-10-14 1977-04-15 Mitsubishi Electric Corp Real time simulation system of input/output unit
JPS55159257A (en) * 1979-05-30 1980-12-11 Mitsubishi Electric Corp Debugging system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034645U (en) * 1983-08-10 1985-03-09 三菱電機株式会社 Simulated transfer response signal generator

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