JPS569827A - Key input control system - Google Patents

Key input control system

Info

Publication number
JPS569827A
JPS569827A JP8361679A JP8361679A JPS569827A JP S569827 A JPS569827 A JP S569827A JP 8361679 A JP8361679 A JP 8361679A JP 8361679 A JP8361679 A JP 8361679A JP S569827 A JPS569827 A JP S569827A
Authority
JP
Japan
Prior art keywords
depressed
data
key
keys
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8361679A
Other languages
Japanese (ja)
Inventor
Yoji Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP8361679A priority Critical patent/JPS569827A/en
Publication of JPS569827A publication Critical patent/JPS569827A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To reduce the cost and also to perform roll-over operation among all keys by composing a shift key, control key, etc., of circuits under the same matrix control with data keys.
CONSTITUTION: Key matrix 1' is incorporated by using the same element while shift key SK and control key CK are considered to be some of data keys. When data keys except SK and CK are depressed, modes are not changed and when SK and CK are depressed, the modes are changed. Namely, depressing SK or CK sets a corresponding bit of bit memory 6 via multiplexer 3 and FF30 or 31 is set correspondingly, so that the set output of FF30 or 31 will change the address of data memory 4 over to area DM1 or DM2. Therefore, when data keys are depressed after SK is depressed, the address is changed over from DM0 to DM1 and data stored at address DM2 are sent to buffer 7 successively.
COPYRIGHT: (C)1981,JPO&Japio
JP8361679A 1979-07-02 1979-07-02 Key input control system Pending JPS569827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8361679A JPS569827A (en) 1979-07-02 1979-07-02 Key input control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8361679A JPS569827A (en) 1979-07-02 1979-07-02 Key input control system

Publications (1)

Publication Number Publication Date
JPS569827A true JPS569827A (en) 1981-01-31

Family

ID=13807412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8361679A Pending JPS569827A (en) 1979-07-02 1979-07-02 Key input control system

Country Status (1)

Country Link
JP (1) JPS569827A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57187732A (en) * 1981-05-14 1982-11-18 Toshiba Corp Shift control system for keyboard
JPH02309413A (en) * 1989-05-17 1990-12-25 Samsung Electron Co Ltd Scan data conversion circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57187732A (en) * 1981-05-14 1982-11-18 Toshiba Corp Shift control system for keyboard
JPH02309413A (en) * 1989-05-17 1990-12-25 Samsung Electron Co Ltd Scan data conversion circuit

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