JPS5688531A - Data input device - Google Patents

Data input device

Info

Publication number
JPS5688531A
JPS5688531A JP16642379A JP16642379A JPS5688531A JP S5688531 A JPS5688531 A JP S5688531A JP 16642379 A JP16642379 A JP 16642379A JP 16642379 A JP16642379 A JP 16642379A JP S5688531 A JPS5688531 A JP S5688531A
Authority
JP
Japan
Prior art keywords
data
peripheral device
series
sending
detected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16642379A
Other languages
Japanese (ja)
Inventor
Kensuke Uehara
Norihide Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16642379A priority Critical patent/JPS5688531A/en
Publication of JPS5688531A publication Critical patent/JPS5688531A/en
Pending legal-status Critical Current

Links

Landscapes

  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE: To prevent a sending-back peripheral device from being not in operation by inhibiting the supply of data to be detected as a framing error by the peripheral device when supplying series input data to the peripheral device.
CONSTITUTION: Since no framing error is detected as far as series input data supplied is normal, it is converted into parallel data C, which is inputted to arithmetic controller 12 and also supplied to a sending-back peripheral device after being reconverted into series data G, confirming the input information. If a framing error of series input data A is detected, error detecting circuit 14 generates control signals D1 and D2 to close gate circuit 15 while the preset processing of parallel data C to be inputted to arithmetic controller 12 is performed, thereby inhibiting the supply of series data G to the sending-back peripheral device.
COPYRIGHT: (C)1981,JPO&Japio
JP16642379A 1979-12-21 1979-12-21 Data input device Pending JPS5688531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16642379A JPS5688531A (en) 1979-12-21 1979-12-21 Data input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16642379A JPS5688531A (en) 1979-12-21 1979-12-21 Data input device

Publications (1)

Publication Number Publication Date
JPS5688531A true JPS5688531A (en) 1981-07-18

Family

ID=15831142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16642379A Pending JPS5688531A (en) 1979-12-21 1979-12-21 Data input device

Country Status (1)

Country Link
JP (1) JPS5688531A (en)

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