JPS5680734A - Memory system for control program of terminal device - Google Patents

Memory system for control program of terminal device

Info

Publication number
JPS5680734A
JPS5680734A JP15754579A JP15754579A JPS5680734A JP S5680734 A JPS5680734 A JP S5680734A JP 15754579 A JP15754579 A JP 15754579A JP 15754579 A JP15754579 A JP 15754579A JP S5680734 A JPS5680734 A JP S5680734A
Authority
JP
Japan
Prior art keywords
control program
terminal device
ram15
stored
memory system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15754579A
Other languages
Japanese (ja)
Inventor
Setsuo Yoshihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15754579A priority Critical patent/JPS5680734A/en
Publication of JPS5680734A publication Critical patent/JPS5680734A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to modify easily the control program of each terminal device, by providing each terminal device with RAM stored with the control program of the terminal device and a means of checking the control program.
CONSTITUTION: Plural terminal devices 121 (shown only one in the figure) having the same functions or similar functions are controlled by central controller 11. In RAM15, a control program for operating detecting means 161, mechanism driving means 162... of terminal device 121 is stored. When the power source of terminal device 121 is put to work, a check program is read out of ROM17 to check the memory contents of RAM15. If the control program in RAM15 is destroyed, a normal control program is obtained from RAM of another terminal device stored with the normal control program to update the contents of RAM15.
COPYRIGHT: (C)1981,JPO&Japio
JP15754579A 1979-12-05 1979-12-05 Memory system for control program of terminal device Pending JPS5680734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15754579A JPS5680734A (en) 1979-12-05 1979-12-05 Memory system for control program of terminal device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15754579A JPS5680734A (en) 1979-12-05 1979-12-05 Memory system for control program of terminal device

Publications (1)

Publication Number Publication Date
JPS5680734A true JPS5680734A (en) 1981-07-02

Family

ID=15652013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15754579A Pending JPS5680734A (en) 1979-12-05 1979-12-05 Memory system for control program of terminal device

Country Status (1)

Country Link
JP (1) JPS5680734A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59109931A (en) * 1982-12-15 1984-06-25 Omron Tateisi Electronics Co Constant data transferring method of centralized control system
JPS6210746A (en) * 1985-07-08 1987-01-19 Hitachi Cable Ltd Non-volatile ram checking method
JPS62126452A (en) * 1985-11-27 1987-06-08 Hitachi Ltd Memory load system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59109931A (en) * 1982-12-15 1984-06-25 Omron Tateisi Electronics Co Constant data transferring method of centralized control system
JPS6210746A (en) * 1985-07-08 1987-01-19 Hitachi Cable Ltd Non-volatile ram checking method
JPS62126452A (en) * 1985-11-27 1987-06-08 Hitachi Ltd Memory load system

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