JPS5670646U - - Google Patents

Info

Publication number
JPS5670646U
JPS5670646U JP14118480U JP14118480U JPS5670646U JP S5670646 U JPS5670646 U JP S5670646U JP 14118480 U JP14118480 U JP 14118480U JP 14118480 U JP14118480 U JP 14118480U JP S5670646 U JPS5670646 U JP S5670646U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14118480U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14118480U priority Critical patent/JPS5670646U/ja
Publication of JPS5670646U publication Critical patent/JPS5670646U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
JP14118480U 1980-10-03 1980-10-03 Pending JPS5670646U (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14118480U JPS5670646U (ko) 1980-10-03 1980-10-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14118480U JPS5670646U (ko) 1980-10-03 1980-10-03

Publications (1)

Publication Number Publication Date
JPS5670646U true JPS5670646U (ko) 1981-06-11

Family

ID=29372517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14118480U Pending JPS5670646U (ko) 1980-10-03 1980-10-03

Country Status (1)

Country Link
JP (1) JPS5670646U (ko)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226187A (en) * 1975-08-22 1977-02-26 Hitachi Ltd Semiconductor unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226187A (en) * 1975-08-22 1977-02-26 Hitachi Ltd Semiconductor unit

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