JPS5665650U - - Google Patents
Info
- Publication number
- JPS5665650U JPS5665650U JP1979147342U JP14734279U JPS5665650U JP S5665650 U JPS5665650 U JP S5665650U JP 1979147342 U JP1979147342 U JP 1979147342U JP 14734279 U JP14734279 U JP 14734279U JP S5665650 U JPS5665650 U JP S5665650U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979147342U JPS5665650U (en) | 1979-10-23 | 1979-10-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979147342U JPS5665650U (en) | 1979-10-23 | 1979-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5665650U true JPS5665650U (en) | 1981-06-01 |
Family
ID=29378482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1979147342U Pending JPS5665650U (en) | 1979-10-23 | 1979-10-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5665650U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018020640A1 (en) * | 2016-07-28 | 2018-02-01 | 三菱電機株式会社 | Semiconductor device |
-
1979
- 1979-10-23 JP JP1979147342U patent/JPS5665650U/ja active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018020640A1 (en) * | 2016-07-28 | 2018-02-01 | 三菱電機株式会社 | Semiconductor device |
| JPWO2018020640A1 (en) * | 2016-07-28 | 2018-12-13 | 三菱電機株式会社 | Semiconductor device |
| CN109478543A (en) * | 2016-07-28 | 2019-03-15 | 三菱电机株式会社 | Semiconductor device |
| DE112016007096B4 (en) | 2016-07-28 | 2023-06-29 | Mitsubishi Electric Corporation | semiconductor device |
| US12009332B2 (en) | 2016-07-28 | 2024-06-11 | Mitsubishi Electric Corporation | Semiconductor device having high yield strength intermediate plate |