JPS5663673A - Slice level generation system - Google Patents

Slice level generation system

Info

Publication number
JPS5663673A
JPS5663673A JP13834379A JP13834379A JPS5663673A JP S5663673 A JPS5663673 A JP S5663673A JP 13834379 A JP13834379 A JP 13834379A JP 13834379 A JP13834379 A JP 13834379A JP S5663673 A JPS5663673 A JP S5663673A
Authority
JP
Japan
Prior art keywords
signal
circuit
slice level
comparator
video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13834379A
Other languages
Japanese (ja)
Inventor
Ichiro Urano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13834379A priority Critical patent/JPS5663673A/en
Publication of JPS5663673A publication Critical patent/JPS5663673A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the influence by variations caused by the position of a sensor, and variations of the optical system, and obtain an exact video shaping signal, by dividng one scanning section of a optical sensor, and providing a circuit for setting each independent slice level.
CONSTITUTION: A video signal 112 is output by scanning the field of view of the medium 302 by the sensor circuit 12 and converting it photoelectrically, and a video signal 113 is provided to the slice level setting circuits 14, 15 and the comparator 18 through the amplifier counter circuit 13. Also, clocks from the clock osillating circuit 11 are counted by the circuit 19, and a sectional signal and an output signal 119 of the inverting circuit 16 are provided to the circuit 14 and the circuit 15, respectively. Moreover, divided slice level signals 114, 115 from the respective circuits 14, 15 are provided to the analog multiplexer 17, at the same time the sectional signal 118 is provided to the multiplexer 17, and a reference signal 116 is provided to the comparator 18 in accordance with "1" or "0" of the signal 119. And the signals 114, 115 are compared with the signal 116 by the comparator 18, and a video shaping signal which has an equal level corresponding to the mark is output.
COPYRIGHT: (C)1981,JPO&Japio
JP13834379A 1979-10-26 1979-10-26 Slice level generation system Pending JPS5663673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13834379A JPS5663673A (en) 1979-10-26 1979-10-26 Slice level generation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13834379A JPS5663673A (en) 1979-10-26 1979-10-26 Slice level generation system

Publications (1)

Publication Number Publication Date
JPS5663673A true JPS5663673A (en) 1981-05-30

Family

ID=15219695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13834379A Pending JPS5663673A (en) 1979-10-26 1979-10-26 Slice level generation system

Country Status (1)

Country Link
JP (1) JPS5663673A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58189783A (en) * 1982-04-30 1983-11-05 Fuji Electric Co Ltd Pattern discriminator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58189783A (en) * 1982-04-30 1983-11-05 Fuji Electric Co Ltd Pattern discriminator

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