JPS5654607A - Record playback mode control device - Google Patents

Record playback mode control device

Info

Publication number
JPS5654607A
JPS5654607A JP13068179A JP13068179A JPS5654607A JP S5654607 A JPS5654607 A JP S5654607A JP 13068179 A JP13068179 A JP 13068179A JP 13068179 A JP13068179 A JP 13068179A JP S5654607 A JPS5654607 A JP S5654607A
Authority
JP
Japan
Prior art keywords
recording
post
impedance
low
bias current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13068179A
Other languages
Japanese (ja)
Inventor
Masakazu Shimazu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13068179A priority Critical patent/JPS5654607A/en
Publication of JPS5654607A publication Critical patent/JPS5654607A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a good-quality post-recording through a simple constitution and operation, by forming a low-impedance post-recording detecting circuit with the capacitors having a prescribed connection, the logic element and the like.
CONSTITUTION: The switches S1WS6 are switched according to the operation of the post-recording operation element 14, and thus the transistors Q1 and Q2 of the post-recording detecting circuit A are turned on. As a result, the bias current flows through the low-impedance route formed with the capacitor 31 plus the transistors Q1 and Q2 for the positive half cycle of the recording AC bias current supplied from the current source 23. On the other hand, the bias current flows through the low-impedance routh passing through the capacitor 31 and the collector and the base of the transistor Q1 for the period of the negative half cycle since the capactiror 32 and the resistance 33 are connected in parallel to the base of the Q1. In this way, a good-quarity post-recording is possible for the recording by the 1st head 15 and the reproduction by the 2nd head 16 through a simple constitution and operation.
COPYRIGHT: (C)1981,JPO&Japio
JP13068179A 1979-10-09 1979-10-09 Record playback mode control device Pending JPS5654607A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13068179A JPS5654607A (en) 1979-10-09 1979-10-09 Record playback mode control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13068179A JPS5654607A (en) 1979-10-09 1979-10-09 Record playback mode control device

Publications (1)

Publication Number Publication Date
JPS5654607A true JPS5654607A (en) 1981-05-14

Family

ID=15040062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13068179A Pending JPS5654607A (en) 1979-10-09 1979-10-09 Record playback mode control device

Country Status (1)

Country Link
JP (1) JPS5654607A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3502744A1 (en) * 1984-06-27 1986-01-09 Nippon Mektron, Ltd., Tokio/Tokyo FLEXIBLE PCB AND METHOD FOR THEIR PRODUCTION

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3502744A1 (en) * 1984-06-27 1986-01-09 Nippon Mektron, Ltd., Tokio/Tokyo FLEXIBLE PCB AND METHOD FOR THEIR PRODUCTION

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