JPS5654097A - Method of forming bias hole - Google Patents

Method of forming bias hole

Info

Publication number
JPS5654097A
JPS5654097A JP13014079A JP13014079A JPS5654097A JP S5654097 A JPS5654097 A JP S5654097A JP 13014079 A JP13014079 A JP 13014079A JP 13014079 A JP13014079 A JP 13014079A JP S5654097 A JPS5654097 A JP S5654097A
Authority
JP
Japan
Prior art keywords
forming bias
bias hole
hole
forming
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13014079A
Other languages
Japanese (ja)
Inventor
Hikari Kimura
Takashi Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13014079A priority Critical patent/JPS5654097A/en
Publication of JPS5654097A publication Critical patent/JPS5654097A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP13014079A 1979-10-09 1979-10-09 Method of forming bias hole Pending JPS5654097A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13014079A JPS5654097A (en) 1979-10-09 1979-10-09 Method of forming bias hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13014079A JPS5654097A (en) 1979-10-09 1979-10-09 Method of forming bias hole

Publications (1)

Publication Number Publication Date
JPS5654097A true JPS5654097A (en) 1981-05-13

Family

ID=15026912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13014079A Pending JPS5654097A (en) 1979-10-09 1979-10-09 Method of forming bias hole

Country Status (1)

Country Link
JP (1) JPS5654097A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128797A (en) * 1982-01-27 1983-08-01 日本電気株式会社 Method of producing multilayer ceramic board
JPH07176867A (en) * 1993-12-20 1995-07-14 Nec Corp Manufacture of printed wiring board
JP2013545288A (en) * 2010-10-12 2013-12-19 コーニンクレッカ フィリップス エヌ ヴェ Highly reflective coating on LED submount

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128797A (en) * 1982-01-27 1983-08-01 日本電気株式会社 Method of producing multilayer ceramic board
JPH07176867A (en) * 1993-12-20 1995-07-14 Nec Corp Manufacture of printed wiring board
JP2013545288A (en) * 2010-10-12 2013-12-19 コーニンクレッカ フィリップス エヌ ヴェ Highly reflective coating on LED submount

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