JPS565336Y2 - - Google Patents
Info
- Publication number
- JPS565336Y2 JPS565336Y2 JP13968175U JP13968175U JPS565336Y2 JP S565336 Y2 JPS565336 Y2 JP S565336Y2 JP 13968175 U JP13968175 U JP 13968175U JP 13968175 U JP13968175 U JP 13968175U JP S565336 Y2 JPS565336 Y2 JP S565336Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Combinations Of Printed Boards (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13968175U JPS565336Y2 (https=) | 1975-10-14 | 1975-10-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13968175U JPS565336Y2 (https=) | 1975-10-14 | 1975-10-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5252650U JPS5252650U (https=) | 1977-04-15 |
| JPS565336Y2 true JPS565336Y2 (https=) | 1981-02-05 |
Family
ID=28619525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13968175U Expired JPS565336Y2 (https=) | 1975-10-14 | 1975-10-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS565336Y2 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4894706A (en) * | 1985-02-14 | 1990-01-16 | Nippon Telegraph And Telephone Corporation | Three-dimensional packaging of semiconductor device chips |
-
1975
- 1975-10-14 JP JP13968175U patent/JPS565336Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5252650U (https=) | 1977-04-15 |