JPS5652426A - Microprocessor unit - Google Patents

Microprocessor unit

Info

Publication number
JPS5652426A
JPS5652426A JP12831379A JP12831379A JPS5652426A JP S5652426 A JPS5652426 A JP S5652426A JP 12831379 A JP12831379 A JP 12831379A JP 12831379 A JP12831379 A JP 12831379A JP S5652426 A JPS5652426 A JP S5652426A
Authority
JP
Japan
Prior art keywords
circuit
speed processing
electric power
clock signal
high speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12831379A
Other languages
Japanese (ja)
Inventor
Yasuhiro Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12831379A priority Critical patent/JPS5652426A/en
Publication of JPS5652426A publication Critical patent/JPS5652426A/en
Pending legal-status Critical Current

Links

Landscapes

  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE: To reduce the current comsumption by stopping except when required, operation of the high speed processing part of the microprocessor CPU consisting of a part which requires a high speed processing and a part for which a slow speed processing will do.
CONSTITUTION: In a radio selective calling receiver, a signal which has been received, detected 2 and shaped to a square is decoded by CPU5, and drives a calling horn 8 through the buffer 7. CPU5 is connected to the 3V electric power source 6, and consists of a low speed processing block 15 which counts a clock signal from the oscillating circuit 17 of low frequency, and a high speed processing block 19 which is formed by an oscillating circuit 25 generating a clock signal of high frequency, and a processing circuit 21 executing decoding, storage and operation. Whenever the counting value of the circuit 18 reaches the fixed value, a clock signal from the circuit 25 is provided to the circuit 21, the switching circuit 9 is controlled by a short time decided by the circuit 21, 1V electric power source 10 is applied to the unit only at the time of receiving operation, and the current consumption is reduced by intermittently performing the electric power supply to the unit.
COPYRIGHT: (C)1981,JPO&Japio
JP12831379A 1979-10-03 1979-10-03 Microprocessor unit Pending JPS5652426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12831379A JPS5652426A (en) 1979-10-03 1979-10-03 Microprocessor unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12831379A JPS5652426A (en) 1979-10-03 1979-10-03 Microprocessor unit

Publications (1)

Publication Number Publication Date
JPS5652426A true JPS5652426A (en) 1981-05-11

Family

ID=14981677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12831379A Pending JPS5652426A (en) 1979-10-03 1979-10-03 Microprocessor unit

Country Status (1)

Country Link
JP (1) JPS5652426A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368051A (en) * 1976-11-29 1978-06-17 Sharp Corp Integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368051A (en) * 1976-11-29 1978-06-17 Sharp Corp Integrated circuit device

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