JPS5651145A - Circuit adapter for wide band high level data link communication - Google Patents

Circuit adapter for wide band high level data link communication

Info

Publication number
JPS5651145A
JPS5651145A JP13573780A JP13573780A JPS5651145A JP S5651145 A JPS5651145 A JP S5651145A JP 13573780 A JP13573780 A JP 13573780A JP 13573780 A JP13573780 A JP 13573780A JP S5651145 A JPS5651145 A JP S5651145A
Authority
JP
Japan
Prior art keywords
high level
data link
level data
wide band
link communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13573780A
Other languages
English (en)
Other versions
JPH0357667B2 (ja
Inventor
Shii Reimondo Jieemusu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of JPS5651145A publication Critical patent/JPS5651145A/ja
Publication of JPH0357667B2 publication Critical patent/JPH0357667B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
JP13573780A 1979-09-28 1980-09-29 Circuit adapter for wide band high level data link communication Granted JPS5651145A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/079,961 US4261035A (en) 1979-09-28 1979-09-28 Broadband high level data link communication line adapter

Publications (2)

Publication Number Publication Date
JPS5651145A true JPS5651145A (en) 1981-05-08
JPH0357667B2 JPH0357667B2 (ja) 1991-09-02

Family

ID=22153922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13573780A Granted JPS5651145A (en) 1979-09-28 1980-09-29 Circuit adapter for wide band high level data link communication

Country Status (7)

Country Link
US (1) US4261035A (ja)
JP (1) JPS5651145A (ja)
AU (1) AU539541B2 (ja)
BE (1) BE885417A (ja)
CA (1) CA1150847A (ja)
CH (1) CH645470A5 (ja)
DE (1) DE3035506A1 (ja)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58501602A (ja) * 1981-09-18 1983-09-22 クリスチャン　ロプシング　エ−・エス マルチプロセッサ・コンピュ−タシステム
EP0113166A3 (en) * 1982-09-30 1986-10-29 Honeywell Information Systems Inc. Interactive data processing system
US4510581A (en) * 1983-02-14 1985-04-09 Prime Computer, Inc. High speed buffer allocation apparatus
US4642755A (en) * 1983-03-31 1987-02-10 At&T Bell Laboratories Shared memory with two distinct addressing structures
US4644547A (en) * 1984-06-28 1987-02-17 Westinghouse Electric Corp. Digital message format for two-way communication and control network
EP0244544B1 (en) * 1986-04-30 1991-01-16 International Business Machines Corporation Very high speed line adapter for a communication controller
DE3683160D1 (de) * 1986-10-29 1992-02-06 Ibm Empfangs- und sendemechanismen fuer die leitungsabtaster einer uebertragungssteuerung.
US5241660A (en) * 1986-10-30 1993-08-31 National Semiconductor Corporation Buffered asynchronous communications element with receive/transmit control and status reporting
US4823312A (en) * 1986-10-30 1989-04-18 National Semiconductor Corp. Asynchronous communications element
US4958342A (en) * 1987-03-11 1990-09-18 Aristacom International, Inc. Adaptive digital network interface
US4882727A (en) * 1987-03-11 1989-11-21 Aristacom International, Inc. Adaptive digital network interface
US4890254A (en) * 1987-03-11 1989-12-26 Aristacom International, Inc. Clock disabling circuit
US4855948A (en) * 1987-10-08 1989-08-08 International Business Machines Corporation Bypass booster mechanisms for the line scanners of a communication controller
EP0325077B1 (en) * 1988-01-22 1992-09-09 International Business Machines Corporation Scanner interface for the line adapters of a communication controller
US5155810A (en) * 1989-01-10 1992-10-13 Bull Hn Information Systems Inc. Dual FIFO peripheral with combinatorial logic circuitry
US5274762A (en) * 1989-12-15 1993-12-28 Ncr Corporation Method for high speed data transfer
US5255372A (en) * 1990-08-31 1993-10-19 International Business Machines Corporation Apparatus for efficiently interconnecing channels of a multiprocessor system multiplexed via channel adapters
US5537624A (en) * 1991-02-12 1996-07-16 The United States Of America As Represented By The Secretary Of The Navy Data repacking circuit having toggle buffer for transferring digital data from P1Q1 bus width to P2Q2 bus width
US5517533A (en) * 1992-03-04 1996-05-14 Digital Equipment Corporation Parallel implementation of run length coding apparatus and method
US5412782A (en) 1992-07-02 1995-05-02 3Com Corporation Programmed I/O ethernet adapter with early interrupts for accelerating data transfer
US5414740A (en) * 1992-12-17 1995-05-09 International Business Machines Corporation Synchronous communication system having multiplexed information transfer and transition phases
DE69330399T2 (de) * 1992-12-18 2002-05-02 Advanced Micro Devices Inc HDLC-Empfänger
CA2107046A1 (en) * 1993-01-08 1994-07-09 James Allan Kahle Method and system for increased instruction dispatch efficiency in superscalar processor system
US5428611A (en) * 1993-05-28 1995-06-27 Digital Equipment Corporation Strong framing protocol for HDLC and other run-length codes
US5553228A (en) * 1994-09-19 1996-09-03 International Business Machines Corporation Accelerated interface between processors and hardware adapters
US6314485B1 (en) * 1997-11-14 2001-11-06 Agere Systems Guardian Corp. Automatic status register
US7206881B2 (en) * 2002-09-16 2007-04-17 Telefonaktiebolaget Lm Ericsson (Publ) Arrangement and method for controlling dataflow on a data bus
US6907484B2 (en) * 2002-09-24 2005-06-14 Sun Microsystems, Inc Method and apparatus for atomically changing selected bits within a register

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5416143A (en) * 1977-05-18 1979-02-06 Honeywell Inf Systems Partial byte receiver for digital communication
JPS5459007A (en) * 1977-10-04 1979-05-12 Ncr Co Digital communication field size modifying system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1323048A (en) * 1971-03-03 1973-07-11 Ibm Communications control unit
FR2257112B1 (ja) * 1974-01-03 1977-06-24 Honeywell Bull Soc Ind
US4204888A (en) * 1975-05-19 1980-05-27 The Foundation: The Research Institute Of Electric And Magnetic Alloys High damping capacity alloy
US4071887A (en) * 1975-10-30 1978-01-31 Motorola, Inc. Synchronous serial data adaptor
US4124888A (en) * 1975-12-24 1978-11-07 Computer Automation, Inc. Peripheral-unit controller apparatus
US4133030A (en) * 1977-01-19 1979-01-02 Honeywell Information Systems Inc. Control system providing for the transfer of data in a communications processing system employing channel dedicated control blocks

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5416143A (en) * 1977-05-18 1979-02-06 Honeywell Inf Systems Partial byte receiver for digital communication
JPS5459007A (en) * 1977-10-04 1979-05-12 Ncr Co Digital communication field size modifying system

Also Published As

Publication number Publication date
CH645470A5 (fr) 1984-09-28
JPH0357667B2 (ja) 1991-09-02
US4261035A (en) 1981-04-07
BE885417A (fr) 1981-01-16
AU6150480A (en) 1981-03-26
AU539541B2 (en) 1984-10-04
CA1150847A (en) 1983-07-26
DE3035506A1 (de) 1981-07-02

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