JPS5649389B2 - - Google Patents

Info

Publication number
JPS5649389B2
JPS5649389B2 JP8889773A JP8889773A JPS5649389B2 JP S5649389 B2 JPS5649389 B2 JP S5649389B2 JP 8889773 A JP8889773 A JP 8889773A JP 8889773 A JP8889773 A JP 8889773A JP S5649389 B2 JPS5649389 B2 JP S5649389B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8889773A
Other languages
Japanese (ja)
Other versions
JPS4973938A (US07922777-20110412-C00004.png
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4973938A publication Critical patent/JPS4973938A/ja
Publication of JPS5649389B2 publication Critical patent/JPS5649389B2/ja
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/601Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP8889773A 1972-10-05 1973-08-09 Expired JPS5649389B2 (US07922777-20110412-C00004.png)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00295301A US3820078A (en) 1972-10-05 1972-10-05 Multi-level storage system having a buffer store with variable mapping modes

Publications (2)

Publication Number Publication Date
JPS4973938A JPS4973938A (US07922777-20110412-C00004.png) 1974-07-17
JPS5649389B2 true JPS5649389B2 (US07922777-20110412-C00004.png) 1981-11-21

Family

ID=23137115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8889773A Expired JPS5649389B2 (US07922777-20110412-C00004.png) 1972-10-05 1973-08-09

Country Status (6)

Country Link
US (1) US3820078A (US07922777-20110412-C00004.png)
JP (1) JPS5649389B2 (US07922777-20110412-C00004.png)
CA (1) CA995823A (US07922777-20110412-C00004.png)
DE (1) DE2350215C2 (US07922777-20110412-C00004.png)
FR (1) FR2202616A5 (US07922777-20110412-C00004.png)
GB (1) GB1432848A (US07922777-20110412-C00004.png)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662488U (US07922777-20110412-C00004.png) * 1979-10-19 1981-05-26
JPS645053Y2 (US07922777-20110412-C00004.png) * 1982-03-11 1989-02-08

Families Citing this family (48)

* Cited by examiner, † Cited by third party
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US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
JPS5226124A (en) * 1975-08-22 1977-02-26 Fujitsu Ltd Buffer memory control unit
FR2344094A1 (fr) * 1976-03-10 1977-10-07 Cii Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires
US4128882A (en) * 1976-08-19 1978-12-05 Massachusetts Institute Of Technology Packet memory system with hierarchical structure
US4075686A (en) * 1976-12-30 1978-02-21 Honeywell Information Systems Inc. Input/output cache system including bypass capability
US4084234A (en) * 1977-02-17 1978-04-11 Honeywell Information Systems Inc. Cache write capacity
US4084236A (en) * 1977-02-18 1978-04-11 Honeywell Information Systems Inc. Error detection and correction capability for a memory system
US4214303A (en) * 1977-12-22 1980-07-22 Honeywell Information Systems Inc. Word oriented high speed buffer memory system connected to a system bus
US4157587A (en) * 1977-12-22 1979-06-05 Honeywell Information Systems Inc. High speed buffer memory system with word prefetch
US4195343A (en) * 1977-12-22 1980-03-25 Honeywell Information Systems Inc. Round robin replacement for a cache store
US4161024A (en) * 1977-12-22 1979-07-10 Honeywell Information Systems Inc. Private cache-to-CPU interface in a bus oriented data processing system
US4399503A (en) * 1978-06-30 1983-08-16 Bunker Ramo Corporation Dynamic disk buffer control unit
US4213182A (en) * 1978-12-06 1980-07-15 General Electric Company Programmable energy load controller system and methods
US4268907A (en) * 1979-01-22 1981-05-19 Honeywell Information Systems Inc. Cache unit bypass apparatus
US4217640A (en) * 1978-12-11 1980-08-12 Honeywell Information Systems Inc. Cache unit with transit block buffer apparatus
US4298929A (en) * 1979-01-26 1981-11-03 International Business Machines Corporation Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability
US4511895A (en) * 1979-10-30 1985-04-16 General Electric Company Method and apparatus for controlling distributed electrical loads
US4317168A (en) * 1979-11-23 1982-02-23 International Business Machines Corporation Cache organization enabling concurrent line castout and line fetch transfers with main storage
US4315312A (en) * 1979-12-19 1982-02-09 Ncr Corporation Cache memory having a variable data block size
US4382278A (en) * 1980-06-05 1983-05-03 Texas Instruments Incorporated Hierarchial memory system with microcommand memory and pointer register mapping virtual CPU registers in workspace cache #4 and main memory cache
US4472772A (en) * 1981-08-03 1984-09-18 Burroughs Corporation High speed microinstruction execution apparatus
US4533995A (en) * 1981-08-03 1985-08-06 International Business Machines Corporation Method and system for handling sequential data in a hierarchical store
US4458310A (en) * 1981-10-02 1984-07-03 At&T Bell Laboratories Cache memory using a lowest priority replacement circuit
US4503501A (en) * 1981-11-27 1985-03-05 Storage Technology Corporation Adaptive domain partitioning of cache memory space
US4464717A (en) * 1982-03-31 1984-08-07 Honeywell Information Systems Inc. Multilevel cache system with graceful degradation capability
US4887235A (en) * 1982-12-17 1989-12-12 Symbolics, Inc. Symbolic language data processing system
US4747070A (en) * 1984-01-09 1988-05-24 Wang Laboratories, Inc. Reconfigurable memory system
JPS60205760A (ja) * 1984-03-30 1985-10-17 Fuji Xerox Co Ltd メモリ制御装置
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
JPH0673114B2 (ja) * 1987-03-31 1994-09-14 日本電気株式会社 キヤツシユ制御装置
US4833601A (en) * 1987-05-28 1989-05-23 Bull Hn Information Systems Inc. Cache resiliency in processing a variety of address faults
US5115496A (en) * 1988-01-26 1992-05-19 Nec Corporation Queue device capable of quickly transferring a digital signal unit of a word length different from a single word length
KR900008516A (ko) * 1988-11-01 1990-06-04 미다 가쓰시게 버퍼 기억장치
US5202969A (en) * 1988-11-01 1993-04-13 Hitachi, Ltd. Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively
EP0375864A3 (en) * 1988-12-29 1991-03-20 International Business Machines Corporation Cache bypass
US5070502A (en) * 1989-06-23 1991-12-03 Digital Equipment Corporation Defect tolerant set associative cache
FR2652926B1 (fr) * 1989-10-06 1994-07-08 Bull Sa Procede d'exploitation de la memoire dans un systeme informatique du type a adressage virtuel et dispositif pour la mise en óoeuvre dudit procede.
US5276832A (en) * 1990-06-19 1994-01-04 Dell U.S.A., L.P. Computer system having a selectable cache subsystem
US5454093A (en) * 1991-02-25 1995-09-26 International Business Machines Corporation Buffer bypass for quick data access
US5606681A (en) * 1994-03-02 1997-02-25 Eec Systems, Inc. Method and device implementing software virtual disk in computer RAM that uses a cache of IRPs to increase system performance
US5931945A (en) * 1994-04-29 1999-08-03 Sun Microsystems, Inc. Graphic system for masking multiple non-contiguous bytes having decode logic to selectively activate each of the control lines based on the mask register bits
US5577226A (en) 1994-05-06 1996-11-19 Eec Systems, Inc. Method and system for coherently caching I/O devices across a network
US5636362A (en) * 1994-09-28 1997-06-03 Intel Corporation Programmable high watermark in stack frame cache using second region as a storage if first region is full and an event having a predetermined minimum priority
US6434665B1 (en) * 1999-10-01 2002-08-13 Stmicroelectronics, Inc. Cache memory store buffer
US6728823B1 (en) * 2000-02-18 2004-04-27 Hewlett-Packard Development Company, L.P. Cache connection with bypassing feature
US6792484B1 (en) * 2000-07-28 2004-09-14 Marconi Communications, Inc. Method and apparatus for storing data using a plurality of queues
TW201015579A (en) * 2008-09-18 2010-04-16 Panasonic Corp Buffer memory device, memory system, and data readout method
US9274971B2 (en) 2012-11-27 2016-03-01 International Business Machines Corporation Low latency data exchange

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR10582E (fr) * 1970-06-29 1909-07-30 Paul Alexis Victor Lerolle Jeu de serrures avec passe-partout

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662488U (US07922777-20110412-C00004.png) * 1979-10-19 1981-05-26
JPS645053Y2 (US07922777-20110412-C00004.png) * 1982-03-11 1989-02-08

Also Published As

Publication number Publication date
CA995823A (en) 1976-08-24
GB1432848A (en) 1976-04-22
DE2350215C2 (de) 1986-09-04
DE2350215A1 (de) 1974-04-18
US3820078A (en) 1974-06-25
FR2202616A5 (US07922777-20110412-C00004.png) 1974-05-03
JPS4973938A (US07922777-20110412-C00004.png) 1974-07-17

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