JPS564864A - Address control unit - Google Patents

Address control unit

Info

Publication number
JPS564864A
JPS564864A JP7988479A JP7988479A JPS564864A JP S564864 A JPS564864 A JP S564864A JP 7988479 A JP7988479 A JP 7988479A JP 7988479 A JP7988479 A JP 7988479A JP S564864 A JPS564864 A JP S564864A
Authority
JP
Japan
Prior art keywords
address
value
counter
counters
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7988479A
Other languages
Japanese (ja)
Inventor
Masaya Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7988479A priority Critical patent/JPS564864A/en
Publication of JPS564864A publication Critical patent/JPS564864A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable various scannings with the clock rate, by providing every two counters toward X, Y directions for the segment scanning, adding the value with addition and performing the vector scanning with other adder.
CONSTITUTION: The X, Y direction main address counters 1a, 1c represent the X, Y direction segment head address at segment scanning and the X, Y direction subsidiary address counters 1b, 1d show the X and Y direction address in the segment. The count value of the main and subsidiary is added at the adders 2a, 2b, and when the value is taken as the address controller outputs 32, 33, the absolute address of X-Y two dimensional picture plane is obtained as the counter value. At vector scanning, the X direction address is the sum of the counters 1a and 1b and the Y direction address increases the value of the counter 1d by 1 when the value of the counter 1b is equal to the value loaded in the latch 4b by using the comparator 3b and the counter 1d, and it is summed with the counter 1c.
COPYRIGHT: (C)1981,JPO&Japio
JP7988479A 1979-06-22 1979-06-22 Address control unit Pending JPS564864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7988479A JPS564864A (en) 1979-06-22 1979-06-22 Address control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7988479A JPS564864A (en) 1979-06-22 1979-06-22 Address control unit

Publications (1)

Publication Number Publication Date
JPS564864A true JPS564864A (en) 1981-01-19

Family

ID=13702674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7988479A Pending JPS564864A (en) 1979-06-22 1979-06-22 Address control unit

Country Status (1)

Country Link
JP (1) JPS564864A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149554A (en) * 1983-02-08 1984-08-27 Toshiba Corp Space filtering device
JPH0391045A (en) * 1989-09-04 1991-04-16 Sharp Corp Address generating circuit for picture memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149554A (en) * 1983-02-08 1984-08-27 Toshiba Corp Space filtering device
JPH0391045A (en) * 1989-09-04 1991-04-16 Sharp Corp Address generating circuit for picture memory

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