JPS56168711U - - Google Patents
Info
- Publication number
- JPS56168711U JPS56168711U JP5965181U JP5965181U JPS56168711U JP S56168711 U JPS56168711 U JP S56168711U JP 5965181 U JP5965181 U JP 5965181U JP 5965181 U JP5965181 U JP 5965181U JP S56168711 U JPS56168711 U JP S56168711U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Ovens (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5965181U JPS56168711U (enrdf_load_stackoverflow) | 1981-04-23 | 1981-04-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5965181U JPS56168711U (enrdf_load_stackoverflow) | 1981-04-23 | 1981-04-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56168711U true JPS56168711U (enrdf_load_stackoverflow) | 1981-12-14 |
Family
ID=29654121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5965181U Pending JPS56168711U (enrdf_load_stackoverflow) | 1981-04-23 | 1981-04-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56168711U (enrdf_load_stackoverflow) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6965262B2 (en) | 1999-10-19 | 2005-11-15 | Rambus Inc. | Method and apparatus for receiving high speed signals with low latency |
US7093145B2 (en) | 1999-10-19 | 2006-08-15 | Rambus Inc. | Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals |
US7362800B1 (en) | 2002-07-12 | 2008-04-22 | Rambus Inc. | Auto-configured equalizer |
US7508871B2 (en) | 2002-07-12 | 2009-03-24 | Rambus Inc. | Selectable-tap equalizer |
US8861667B1 (en) | 2002-07-12 | 2014-10-14 | Rambus Inc. | Clock data recovery circuit with equalizer clock calibration |
-
1981
- 1981-04-23 JP JP5965181U patent/JPS56168711U/ja active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6965262B2 (en) | 1999-10-19 | 2005-11-15 | Rambus Inc. | Method and apparatus for receiving high speed signals with low latency |
US7093145B2 (en) | 1999-10-19 | 2006-08-15 | Rambus Inc. | Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals |
US7124221B1 (en) | 1999-10-19 | 2006-10-17 | Rambus Inc. | Low latency multi-level communication interface |
US7456778B2 (en) | 1999-10-19 | 2008-11-25 | Rambus Inc. | Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals |
US7626442B2 (en) | 1999-10-19 | 2009-12-01 | Rambus Inc. | Low latency multi-level communication interface |
US7362800B1 (en) | 2002-07-12 | 2008-04-22 | Rambus Inc. | Auto-configured equalizer |
US7508871B2 (en) | 2002-07-12 | 2009-03-24 | Rambus Inc. | Selectable-tap equalizer |
US8861667B1 (en) | 2002-07-12 | 2014-10-14 | Rambus Inc. | Clock data recovery circuit with equalizer clock calibration |