JPS56164650U - - Google Patents
Info
- Publication number
- JPS56164650U JPS56164650U JP6356780U JP6356780U JPS56164650U JP S56164650 U JPS56164650 U JP S56164650U JP 6356780 U JP6356780 U JP 6356780U JP 6356780 U JP6356780 U JP 6356780U JP S56164650 U JPS56164650 U JP S56164650U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Iron Core Of Rotating Electric Machines (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6356780U JPS56164650U (OSRAM) | 1980-05-08 | 1980-05-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6356780U JPS56164650U (OSRAM) | 1980-05-08 | 1980-05-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56164650U true JPS56164650U (OSRAM) | 1981-12-07 |
Family
ID=29657792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6356780U Pending JPS56164650U (OSRAM) | 1980-05-08 | 1980-05-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56164650U (OSRAM) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6965262B2 (en) | 1999-10-19 | 2005-11-15 | Rambus Inc. | Method and apparatus for receiving high speed signals with low latency |
| US7093145B2 (en) | 1999-10-19 | 2006-08-15 | Rambus Inc. | Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals |
| US7362800B1 (en) | 2002-07-12 | 2008-04-22 | Rambus Inc. | Auto-configured equalizer |
| US7508871B2 (en) | 2002-07-12 | 2009-03-24 | Rambus Inc. | Selectable-tap equalizer |
| US8861667B1 (en) | 2002-07-12 | 2014-10-14 | Rambus Inc. | Clock data recovery circuit with equalizer clock calibration |
-
1980
- 1980-05-08 JP JP6356780U patent/JPS56164650U/ja active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6965262B2 (en) | 1999-10-19 | 2005-11-15 | Rambus Inc. | Method and apparatus for receiving high speed signals with low latency |
| US7093145B2 (en) | 1999-10-19 | 2006-08-15 | Rambus Inc. | Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals |
| US7124221B1 (en) | 1999-10-19 | 2006-10-17 | Rambus Inc. | Low latency multi-level communication interface |
| US7126408B2 (en) | 1999-10-19 | 2006-10-24 | Rambus Inc. | Method and apparatus for receiving high-speed signals with low latency |
| US7456778B2 (en) | 1999-10-19 | 2008-11-25 | Rambus Inc. | Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals |
| US7362800B1 (en) | 2002-07-12 | 2008-04-22 | Rambus Inc. | Auto-configured equalizer |
| US7508871B2 (en) | 2002-07-12 | 2009-03-24 | Rambus Inc. | Selectable-tap equalizer |
| US8861667B1 (en) | 2002-07-12 | 2014-10-14 | Rambus Inc. | Clock data recovery circuit with equalizer clock calibration |