JPS56111358A - Signal control circuit - Google Patents

Signal control circuit

Info

Publication number
JPS56111358A
JPS56111358A JP1410480A JP1410480A JPS56111358A JP S56111358 A JPS56111358 A JP S56111358A JP 1410480 A JP1410480 A JP 1410480A JP 1410480 A JP1410480 A JP 1410480A JP S56111358 A JPS56111358 A JP S56111358A
Authority
JP
Japan
Prior art keywords
signal
received
circuit
output
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1410480A
Other languages
Japanese (ja)
Inventor
Eiichiro Murata
Manabu Yamane
Koichi Inoue
Tetsuaki Nakanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1410480A priority Critical patent/JPS56111358A/en
Publication of JPS56111358A publication Critical patent/JPS56111358A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
    • H04L27/2272—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals using phase locked loops

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Communication Control (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE:To prevent malfunction even if an undesired signal in a different modulation form is received, by exercising squelch control over a received output signal according to the magnitude of a synchronizing signal such as a signal for bit synchronism. CONSTITUTION:A received signal supplied to receiving input terminal 1 is amplified by amplifier 2 and frequency-converted. Then, it is converted by waveform shaping circuit 3 into a rectangular wave, which is demodulated by the PSK demodulated by the PSK demodulating circuit consisting of phase difference detecting circuit 4, voltage-controlled oscillator 7, amplifier 8, waveform shaping circuit 9, etc., so that its output will be led to terminal 15 by way of data demodulation part 12, D/A converter 13 and analog switch 14. On the other hand, a bit-synchronizing signal included in a basic band signal is doubled by full-wave rectifying circuit 16 and its level is detected by detector 20 to control switch 14 with the output of a comparison with reference value 22 supplied from comparator 21.
JP1410480A 1980-02-06 1980-02-06 Signal control circuit Pending JPS56111358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1410480A JPS56111358A (en) 1980-02-06 1980-02-06 Signal control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1410480A JPS56111358A (en) 1980-02-06 1980-02-06 Signal control circuit

Publications (1)

Publication Number Publication Date
JPS56111358A true JPS56111358A (en) 1981-09-03

Family

ID=11851805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1410480A Pending JPS56111358A (en) 1980-02-06 1980-02-06 Signal control circuit

Country Status (1)

Country Link
JP (1) JPS56111358A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6338436U (en) * 1986-08-27 1988-03-12

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5471502A (en) * 1977-11-18 1979-06-08 Fujitsu Ltd Alarm circuit for photo reception

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5471502A (en) * 1977-11-18 1979-06-08 Fujitsu Ltd Alarm circuit for photo reception

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6338436U (en) * 1986-08-27 1988-03-12

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