JPS5610822B2 - - Google Patents
Info
- Publication number
- JPS5610822B2 JPS5610822B2 JP1034375A JP1034375A JPS5610822B2 JP S5610822 B2 JPS5610822 B2 JP S5610822B2 JP 1034375 A JP1034375 A JP 1034375A JP 1034375 A JP1034375 A JP 1034375A JP S5610822 B2 JPS5610822 B2 JP S5610822B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Mobile Radio Communication Systems (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1034375A JPS5610822B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1975-01-24 | 1975-01-24 | |
| US05/651,778 US4004090A (en) | 1975-01-24 | 1976-01-23 | Bit synchronization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1034375A JPS5610822B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1975-01-24 | 1975-01-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5185660A JPS5185660A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1976-07-27 |
| JPS5610822B2 true JPS5610822B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1981-03-10 |
Family
ID=11747528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1034375A Expired JPS5610822B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1975-01-24 | 1975-01-24 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4004090A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
| JP (1) | JPS5610822B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2410920A1 (fr) * | 1977-11-30 | 1979-06-29 | Materiel Telephonique | Systeme de recuperation d'horloge pour recepteur de transmission de donnees |
| JPS54124612A (en) * | 1978-03-22 | 1979-09-27 | Nippon Telegr & Teleph Corp <Ntt> | Receiving data detector circuit in data transmission |
| USRE36803E (en) * | 1980-04-22 | 2000-08-01 | Sony Corporation | Bit clock reproducing circuit |
| JPS56160157A (en) * | 1980-04-22 | 1981-12-09 | Sony Corp | Bit clock reproducing circuit |
| US4450573A (en) * | 1981-12-07 | 1984-05-22 | Motorola Inc. | Bit data operated squelch |
| US4455664A (en) * | 1981-12-07 | 1984-06-19 | Motorola Inc. | Carrier data operated squelch |
| US4694472A (en) * | 1982-04-26 | 1987-09-15 | American Telephone And Telegraph Company | Clock adjustment method and apparatus for synchronous data communications |
| FR2593008B1 (fr) * | 1986-01-10 | 1993-05-14 | Lmt Radio Professionelle | Procede et dispositif de regeneration de l'integrite du debit binaire dans un reseau plesiochrone |
| DE3639790A1 (de) * | 1986-11-21 | 1988-06-01 | Licentia Gmbh | Verfahren und anordnung zur dynamischen flankensynchronisierung zweier quasisynchroner signale |
| US5912572A (en) * | 1997-03-28 | 1999-06-15 | Cypress Semiconductor Corp. | Synchronizing clock pulse generator for logic derived clock signals with synchronous clock suspension capability for a programmable device |
| US7249273B2 (en) * | 2003-06-23 | 2007-07-24 | Intel Corporation | Synchronized serial interface |
| US8129924B2 (en) | 2006-11-13 | 2012-03-06 | Cypress Semiconductor Corporation | Stochastic signal density modulation for optical transducer control |
| US8044612B2 (en) * | 2007-01-30 | 2011-10-25 | Cypress Semiconductor Corporation | Method and apparatus for networked illumination devices |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3549804A (en) * | 1969-02-10 | 1970-12-22 | Sanders Associates Inc | Bit sampling in asynchronous buffers |
| JPS5012856B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1969-11-27 | 1975-05-15 | ||
| US3851251A (en) * | 1971-10-25 | 1974-11-26 | Martin Marietta Corp | Receiver method and apparatus |
| US3836726A (en) * | 1971-10-25 | 1974-09-17 | Martin Marietta Corp | Data transmission method and apparatus |
| JPS5242610B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1973-04-18 | 1977-10-25 | ||
| US3894185A (en) * | 1974-03-06 | 1975-07-08 | Xerox Corp | Digital run length synchronizer |
-
1975
- 1975-01-24 JP JP1034375A patent/JPS5610822B2/ja not_active Expired
-
1976
- 1976-01-23 US US05/651,778 patent/US4004090A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4004090A (en) | 1977-01-18 |
| JPS5185660A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1976-07-27 |