JPS56106469A - Facsimile receiving system - Google Patents

Facsimile receiving system

Info

Publication number
JPS56106469A
JPS56106469A JP805980A JP805980A JPS56106469A JP S56106469 A JPS56106469 A JP S56106469A JP 805980 A JP805980 A JP 805980A JP 805980 A JP805980 A JP 805980A JP S56106469 A JPS56106469 A JP S56106469A
Authority
JP
Japan
Prior art keywords
circuit
received
drum
synchronous signal
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP805980A
Other languages
Japanese (ja)
Inventor
Takeo Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP805980A priority Critical patent/JPS56106469A/en
Publication of JPS56106469A publication Critical patent/JPS56106469A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Scanning Arrangements (AREA)
  • Storing Facsimile Image Data (AREA)

Abstract

PURPOSE:To ensure an automatic control for the jitter during the record and thus perform an assured reception of data, by delaying the synchronous signal by the time during which the received picture signals fill the full memory capacity of the temporary memory means. CONSTITUTION:The received picture signals are stored in the temporary memory 5 having a capacity to store the picture signals equivalent to a rotation of the drum. The reception control circuit 3 detects the print start, print stop and drum rotation signals out of the received signals. The synchronous circuit 4 applies the synchronous signal received from the demodulator circuit 1 to the delay circuit 11 after the input of the start signal. The circuit 11 and the delay circuit 10 that imputs the end signal have the delay characteristics corresponding to the drum rotational phases of 180 deg. and 360 deg. each. On the other hand, the synchronous signal supplied from the drum of the reception side is applied to the phase difference detection circuit 13 to receive a detection of the phase to the received synchronous signal received from the circuit 11. With this output of detection, the drum control circuit is controlled to ensure an automatic control of the jitter occurring in the recording.
JP805980A 1980-01-25 1980-01-25 Facsimile receiving system Pending JPS56106469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP805980A JPS56106469A (en) 1980-01-25 1980-01-25 Facsimile receiving system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP805980A JPS56106469A (en) 1980-01-25 1980-01-25 Facsimile receiving system

Publications (1)

Publication Number Publication Date
JPS56106469A true JPS56106469A (en) 1981-08-24

Family

ID=11682755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP805980A Pending JPS56106469A (en) 1980-01-25 1980-01-25 Facsimile receiving system

Country Status (1)

Country Link
JP (1) JPS56106469A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5896455A (en) * 1981-12-04 1983-06-08 Hitachi Ltd Recording for facsimile receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5896455A (en) * 1981-12-04 1983-06-08 Hitachi Ltd Recording for facsimile receiver

Similar Documents

Publication Publication Date Title
JPS5636249A (en) Clock reproducing circuit
CA2220523A1 (en) Digital phase detector employing a digitally controllable delay line
JP2566459B2 (en) Elastic buffer circuit
FR2514973A1 (en) DATA TRANSMISSION SYSTEM USING A THREE-PHASE ENERGY LINE
JPS56106469A (en) Facsimile receiving system
US4215348A (en) Method of and system for synchronizing data reception and retransmission aboard communication satellite
US4017895A (en) Method of detecting defects in read out signals, and apparatus for implementing the same
GB2112236A (en) Digital device for clock signal synchronization
EP0425475B1 (en) Data transmission and detection system
CA2062841A1 (en) Apparatus and method for non-stop switching in asynchronous transfer mode
JPS52142415A (en) Control system for facsimile transmitter receiver
US4051537A (en) Facsimile receiving apparatus
GB2077073A (en) Device for eliminating time base variations in video disc player
US4048657A (en) Method and apparatus for synchronizing a facsimile transmission
CA1133993A (en) Circuit for detecting the phase of sampling impulses, particularly for use in the receiving station of a data transmission system
US4253187A (en) Method and apparatus for sequencing two digital signals
US5012493A (en) Phase difference-adjusting circuit
GB1247717A (en) Electronic phasing system
US3968446A (en) Frequency and phase control system
US4023080A (en) Phase synchronizing circuit
JPS6346863A (en) System for receiving picture signal from meteorogical satellite
US3792453A (en) Data storage systems
US4490820A (en) Reception system for key telephone system
SU585624A1 (en) Device for receiving n-divisible phase-modulated signal
JPH063894B2 (en) Asynchronous data conversion circuit