JPS56105545A - Program abnormality signal generating circuit of microcomputer - Google Patents
Program abnormality signal generating circuit of microcomputerInfo
- Publication number
- JPS56105545A JPS56105545A JP692480A JP692480A JPS56105545A JP S56105545 A JPS56105545 A JP S56105545A JP 692480 A JP692480 A JP 692480A JP 692480 A JP692480 A JP 692480A JP S56105545 A JPS56105545 A JP S56105545A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- abnormality
- ist
- address
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To generate an abnormality signal of high response in the event of program abnormality by performing detection of IST abnormality, machine cycle abnormality and address abnormality at every instruction IST. CONSTITUTION:A detection signal P is generated from a microcomputer muCM10 via a gate 7 by an IST fetch synchronizing signal F and a machine cycle MC synchronizing signal M. The IST is sent to an IST nonregistration detecting circuit 1, by which it is collated with the ISTs having been registered. In the event of noncoincidence, an IST nonregistration signal D is emitted and an MC number signal N is also outputted. The signals D and P generates an IST abnormality signal E3 via a gate 6. The signal N is applied to an MC number noncoincidence detecting circuit 2, where the signal N is latched at the timing of the signal P. When the signals M and N differ, an M number noncoincidence signal I is transmitted therefrom and an MC number abnormality signal E1 is outputted via a gate 3. An address is inputted to an address limiter 4, and when it exceeds a predetermined access range, an address range deviation signal L is transmitted, and an address abnormality signal E2 is outputted via a gate 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP692480A JPS56105545A (en) | 1980-01-25 | 1980-01-25 | Program abnormality signal generating circuit of microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP692480A JPS56105545A (en) | 1980-01-25 | 1980-01-25 | Program abnormality signal generating circuit of microcomputer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56105545A true JPS56105545A (en) | 1981-08-22 |
Family
ID=11651786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP692480A Pending JPS56105545A (en) | 1980-01-25 | 1980-01-25 | Program abnormality signal generating circuit of microcomputer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56105545A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04123440U (en) * | 1991-04-20 | 1992-11-09 | 日本電気アイシーマイコンシステム株式会社 | micro computer |
| JP2011256695A (en) * | 2011-01-18 | 2011-12-22 | Irt Corp | Column capital base isolation structure |
-
1980
- 1980-01-25 JP JP692480A patent/JPS56105545A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04123440U (en) * | 1991-04-20 | 1992-11-09 | 日本電気アイシーマイコンシステム株式会社 | micro computer |
| JP2011256695A (en) * | 2011-01-18 | 2011-12-22 | Irt Corp | Column capital base isolation structure |
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