JPS5588103A - Sequence programmer - Google Patents

Sequence programmer

Info

Publication number
JPS5588103A
JPS5588103A JP16143778A JP16143778A JPS5588103A JP S5588103 A JPS5588103 A JP S5588103A JP 16143778 A JP16143778 A JP 16143778A JP 16143778 A JP16143778 A JP 16143778A JP S5588103 A JPS5588103 A JP S5588103A
Authority
JP
Japan
Prior art keywords
memory
user
program
unit
cassette
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16143778A
Other languages
Japanese (ja)
Other versions
JPS592043B2 (en
Inventor
Keisuke Kawashima
Hideaki Nakamura
Yoshitane Saito
Kenji Nishikido
Kiyoto Hirase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP16143778A priority Critical patent/JPS592043B2/en
Publication of JPS5588103A publication Critical patent/JPS5588103A/en
Publication of JPS592043B2 publication Critical patent/JPS592043B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To improve a unit in versatility by using nonvolatile RAM as a memory element stored with a user's program and making the whole memory unit into a cassette.
CONSTITUTION: Sequencer 1, constituting of external input terminal 2, external output terminal 3, keyboard switch 6, user's program memory 4, and CPU5 as shown in the figure, exercises control according to a program in memory 4. Memory 4 consists of nonvolatile memory 15 and the whole memory unit 16 is arranged on printed substrate 13 with connector 12; and corresponding memory 15 is also arranged together with erasure-disable signal generating circuit 19 inhibiting erasure in user's memory 4 and contained in cassette 14. Replacing memory unit 16 allows sequencer 1 in the figure to be applied for various uses.
COPYRIGHT: (C)1980,JPO&Japio
JP16143778A 1978-12-27 1978-12-27 sequence programmer Expired JPS592043B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16143778A JPS592043B2 (en) 1978-12-27 1978-12-27 sequence programmer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16143778A JPS592043B2 (en) 1978-12-27 1978-12-27 sequence programmer

Publications (2)

Publication Number Publication Date
JPS5588103A true JPS5588103A (en) 1980-07-03
JPS592043B2 JPS592043B2 (en) 1984-01-17

Family

ID=15735088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16143778A Expired JPS592043B2 (en) 1978-12-27 1978-12-27 sequence programmer

Country Status (1)

Country Link
JP (1) JPS592043B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445169A (en) * 1980-06-13 1984-04-24 The Tokyo Electric Co., Inc. Sequence display apparatus and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445169A (en) * 1980-06-13 1984-04-24 The Tokyo Electric Co., Inc. Sequence display apparatus and method

Also Published As

Publication number Publication date
JPS592043B2 (en) 1984-01-17

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