JPS5587256A - Fault informing system - Google Patents

Fault informing system

Info

Publication number
JPS5587256A
JPS5587256A JP15933878A JP15933878A JPS5587256A JP S5587256 A JPS5587256 A JP S5587256A JP 15933878 A JP15933878 A JP 15933878A JP 15933878 A JP15933878 A JP 15933878A JP S5587256 A JPS5587256 A JP S5587256A
Authority
JP
Japan
Prior art keywords
fault
contents
area
period
occurrence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15933878A
Other languages
Japanese (ja)
Inventor
Yasushi Ichiki
Hideo Takahashi
Kiminori Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15933878A priority Critical patent/JPS5587256A/en
Publication of JPS5587256A publication Critical patent/JPS5587256A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To exercise secure fault control by reading the contents of a fault-occurrence communication area at fixed period T1 by a master processor, and by writing non-fault information in a corresponding area at every shorter than T1 when no fault is occurring to a slave processor while writing fault-occurrence information when a fault is detected.
CONSTITUTION: In every normal fixed period T1, master processor MCP reads the contents of fault-occurrence communication area A of each slave processor is memory MM and when the contents show a communication pattern, the contents of corresponding fault-content communication area D are read and a needed fault control job is done. Here, period T2 when a slave processor writes non-fault information should be shorter than period T1. Further, when the contents of area A are in an initial set state, it is judged that memory writing operation is impossible.
COPYRIGHT: (C)1980,JPO&Japio
JP15933878A 1978-12-26 1978-12-26 Fault informing system Pending JPS5587256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15933878A JPS5587256A (en) 1978-12-26 1978-12-26 Fault informing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15933878A JPS5587256A (en) 1978-12-26 1978-12-26 Fault informing system

Publications (1)

Publication Number Publication Date
JPS5587256A true JPS5587256A (en) 1980-07-01

Family

ID=15691640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15933878A Pending JPS5587256A (en) 1978-12-26 1978-12-26 Fault informing system

Country Status (1)

Country Link
JP (1) JPS5587256A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023779A (en) * 1982-09-21 1991-06-11 Xerox Corporation Distributed processing environment fault isolation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023779A (en) * 1982-09-21 1991-06-11 Xerox Corporation Distributed processing environment fault isolation

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