JPS558653A - Error detection unit of recording device - Google Patents

Error detection unit of recording device

Info

Publication number
JPS558653A
JPS558653A JP8118578A JP8118578A JPS558653A JP S558653 A JPS558653 A JP S558653A JP 8118578 A JP8118578 A JP 8118578A JP 8118578 A JP8118578 A JP 8118578A JP S558653 A JPS558653 A JP S558653A
Authority
JP
Japan
Prior art keywords
information
circuit
head
bus
recorded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8118578A
Other languages
Japanese (ja)
Inventor
Shukichi Moriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8118578A priority Critical patent/JPS558653A/en
Publication of JPS558653A publication Critical patent/JPS558653A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Magnetic Recording (AREA)

Abstract

PURPOSE: To improve the reliability of recorded information by comparing directly information prior to writing with information recorded on a medium.
CONSTITUTION: When recording information is sent to bus 2 from I/O interface IF1, information is recorded on a medium through modulator circuit 4, bus 5, device IF6 and head 7, and simultaneously, information on bus 2 are stored in 3 successively. Then, reproducing information dependent upon head 8 is supplied to comparison circuit 13 through IF6 and demodulator circuit 10 and is compared with information from circuit 3, and the disagreement output as the comparison result is reported to IF1. Then, circuit 3 covers the time delay between head 7 and head 8.
COPYRIGHT: (C)1980,JPO&Japio
JP8118578A 1978-07-04 1978-07-04 Error detection unit of recording device Pending JPS558653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8118578A JPS558653A (en) 1978-07-04 1978-07-04 Error detection unit of recording device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8118578A JPS558653A (en) 1978-07-04 1978-07-04 Error detection unit of recording device

Publications (1)

Publication Number Publication Date
JPS558653A true JPS558653A (en) 1980-01-22

Family

ID=13739402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8118578A Pending JPS558653A (en) 1978-07-04 1978-07-04 Error detection unit of recording device

Country Status (1)

Country Link
JP (1) JPS558653A (en)

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