JPS558646A - Semiconductor memory circuit - Google Patents

Semiconductor memory circuit

Info

Publication number
JPS558646A
JPS558646A JP8079678A JP8079678A JPS558646A JP S558646 A JPS558646 A JP S558646A JP 8079678 A JP8079678 A JP 8079678A JP 8079678 A JP8079678 A JP 8079678A JP S558646 A JPS558646 A JP S558646A
Authority
JP
Japan
Prior art keywords
potential
information
constitutions
wiring
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8079678A
Other languages
Japanese (ja)
Other versions
JPS5760716B2 (en
Inventor
Masao Suzuki
Toshio Hayashi
Kuniyasu Kawarada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP8079678A priority Critical patent/JPS558646A/en
Publication of JPS558646A publication Critical patent/JPS558646A/en
Publication of JPS5760716B2 publication Critical patent/JPS5760716B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make double access possible and reduce the number of wirings to perform monolithic integration with a high density by connecting transistors to wirings according to prescription. CONSTITUTION:Transistor constitutions Q1 and Q3 and transistor constitutions Q2 and Q4 are made into transistors T13 and T24 having two emitters respectively, and binary information 1 or 0 is stored in Q1 and Q2. Then, if W6 and W7 are made high-potential and low-potential respetively when wiring W5 has a potential higher than wiring W7, T2 (or T1) is turned on, and storage information 1 or 0 is read out according to a current flowing to W5 or not. When W2 is made high- potential under the state where W1 has a potential higher than W3, W3 has a potential higer than W4, and storage information is read out. Further, when W2 is caused to have a potential higher than W4, information rewrite is performed.
JP8079678A 1978-07-03 1978-07-03 Semiconductor memory circuit Granted JPS558646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8079678A JPS558646A (en) 1978-07-03 1978-07-03 Semiconductor memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8079678A JPS558646A (en) 1978-07-03 1978-07-03 Semiconductor memory circuit

Publications (2)

Publication Number Publication Date
JPS558646A true JPS558646A (en) 1980-01-22
JPS5760716B2 JPS5760716B2 (en) 1982-12-21

Family

ID=13728412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8079678A Granted JPS558646A (en) 1978-07-03 1978-07-03 Semiconductor memory circuit

Country Status (1)

Country Link
JP (1) JPS558646A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158908A (en) * 1984-08-31 1986-03-26 Hino Motors Ltd Variable timing movable valve device in internal-combustion engine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158908A (en) * 1984-08-31 1986-03-26 Hino Motors Ltd Variable timing movable valve device in internal-combustion engine

Also Published As

Publication number Publication date
JPS5760716B2 (en) 1982-12-21

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