JPS556133Y2 - - Google Patents
Info
- Publication number
- JPS556133Y2 JPS556133Y2 JP8399671U JP8399671U JPS556133Y2 JP S556133 Y2 JPS556133 Y2 JP S556133Y2 JP 8399671 U JP8399671 U JP 8399671U JP 8399671 U JP8399671 U JP 8399671U JP S556133 Y2 JPS556133 Y2 JP S556133Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8399671U JPS556133Y2 (enExample) | 1971-09-15 | 1971-09-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8399671U JPS556133Y2 (enExample) | 1971-09-15 | 1971-09-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4841160U JPS4841160U (enExample) | 1973-05-25 |
| JPS556133Y2 true JPS556133Y2 (enExample) | 1980-02-12 |
Family
ID=27992716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8399671U Expired JPS556133Y2 (enExample) | 1971-09-15 | 1971-09-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS556133Y2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6288080U (enExample) * | 1985-11-22 | 1987-06-05 | ||
| JPH0760860B2 (ja) * | 1986-06-30 | 1995-06-28 | 富士通株式会社 | 半導体装置 |
| JP5092431B2 (ja) * | 2006-02-03 | 2012-12-05 | 株式会社デンソー | 半導体装置 |
-
1971
- 1971-09-15 JP JP8399671U patent/JPS556133Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4841160U (enExample) | 1973-05-25 |