JPS5558073U - - Google Patents
Info
- Publication number
- JPS5558073U JPS5558073U JP14178178U JP14178178U JPS5558073U JP S5558073 U JPS5558073 U JP S5558073U JP 14178178 U JP14178178 U JP 14178178U JP 14178178 U JP14178178 U JP 14178178U JP S5558073 U JPS5558073 U JP S5558073U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insertion, Bundling And Securing Of Wires For Electric Apparatuses (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14178178U JPS5558073U (en:Method) | 1978-10-16 | 1978-10-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14178178U JPS5558073U (en:Method) | 1978-10-16 | 1978-10-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5558073U true JPS5558073U (en:Method) | 1980-04-19 |
Family
ID=29117909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14178178U Pending JPS5558073U (en:Method) | 1978-10-16 | 1978-10-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5558073U (en:Method) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710758U (en:Method) * | 1980-06-20 | 1982-01-20 |
-
1978
- 1978-10-16 JP JP14178178U patent/JPS5558073U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710758U (en:Method) * | 1980-06-20 | 1982-01-20 |